Designing an Integrated PCI Express System (Versal / UltraScale)
Designing an Integrated PCI Express System (Versal / UltraScale)
Included in this class are modules from PCIe Protocol Overview and Designing with the Versal ACAP: PCI Express Systems
Learn how to implement an AMD Xilinx PCI Express® core in custom applications to improve time to market with the PCIe® core design.
The focus is on:
- Constructing an AMD Xilinx PCI Express system within the customer education reference design
- Enumerating various AMD Xilinx PCI Express core products
- Identifying the advanced capabilities of the PCIe specification
This course also focuses on the AXI Streaming interconnect.
What’s New for 2022.1
- New devices and their PCI Express IPs have been added in overview modules
- Debugging lab now includes debugging the physical layer debugging
- All labs have been updated to the latest software versions
Learn more about PCI Express and AMD Xilinx Technology.
3-Day Instructor-led Course | Price USD | Training Credits |
---|---|---|
Hosted Online - $299/day | $897 | 9 |
In-Person Registration - $399/day | $1197 | 12 |
Printed Course Book (A PDF book is included in the course fee) | $100 | 1 |
Private Training | Contact Us | Contact Us |
Follow on Coaching | Contact Us | Contact Us |
Scheduled Classes
Live Online Training (9am-5pm ET)
Training Duration:
3 Days
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Who should attend:
- Hardware designers who want to create applications using AMD Xilinx IP cores for PCI Express
- Software engineers who want to understand the deeper workings of the AMD Xilinx PCI Express solution
- System architects who want to leverage key AMD Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications
Skills Gained
After completing this comprehensive training, you will know how to:
- Construct a basic PCIe system by:
- Selecting the appropriate core for your application
- Specifying requirements of an endpoint application
- Connecting this endpoint with the core
- Utilizing FPGA resources to support the core
- Simulating the design
- Identify the advanced capabilities of the PCIe specification protocol and feature set
Course Outline
Day 1 | Day 2 | Day 3 |
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Experience with PCIe specification protocol
- Knowledge of VHDL or Verilog
- Some experience with AMD Xilinx implementation tools
- Some experience with a simulation tool, preferably the Vivado® simulator
- Moderate digital design experience