Designing an Integrated PCI Express System (Versal / UltraScale)

Included in this class are modules from PCIe Protocol Overview and Designing with the Versal ACAP: PCI Express Systems

Learn how to implement an AMD Xilinx PCI Express® core in custom applications to improve time to market with the PCIe® core design.

The focus is on:

Constructing an AMD Xilinx PCI Express system within the customer education reference design
Enumerating various AMD Xilinx PCI Express core products
Identifying the advanced capabilities of the PCIe specification

This course also focuses on the AXI Streaming interconnect.

What’s New for 2022.1

New devices and their PCI Express IPs have been added in overview modules
Debugging lab now includes debugging the physical layer debugging
All labs have been updated to the latest software versions

Learn more about PCI Express and AMD Xilinx Technology.

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $299/day	$897	9
In-Person Registration - $399/day	$1197	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Contact Us	Contact Us
Follow on Coaching	Contact Us	Contact Us

Scheduled Classes

Live Online Training (9am-5pm ET)

October 31 - November 2, 2023 | Register Today

May 21-23, 2024 | Register Today

Training Duration:

3 Days

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Who should attend:

Hardware designers who want to create applications using AMD Xilinx IP cores for PCI Express
Software engineers who want to understand the deeper workings of the AMD Xilinx PCI Express solution
System architects who want to leverage key AMD Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications

Skills Gained

After completing this comprehensive training, you will know how to:

Construct a basic PCIe system by:
- Selecting the appropriate core for your application
- Specifying requirements of an endpoint application
- Connecting this endpoint with the core
- Utilizing FPGA resources to support the core
- Simulating the design

Identify the advanced capabilities of the PCIe specification protocol and feature set

Course Outline

Day 1	Day 2	Day 3
Course Introduction Introduction to the PCIe Architecture Review of the PCIe Protocol Packet Formatting Details LAB: Packet Decoding This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Physical Layer, Data Link Layer, and Transaction Layer packets are explored. Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues. Packet Routing Interrupts and Error Management	AMD Xilinx PCI Express Solutions Connecting Logic to the Core PCIe Core Customization Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating an Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs. Packet Formatting Details Simulating a PCIe System Design Lab 2: Simulating the PCIe Core – This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets. Endpoint Application Considerations PCI Express in Embedded Systems Lab 3: Using the PCI Express Core in IP Integrator – This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.	Application Focus: DMA Lab 4: Exploring XDMA – This lab familiarizes you with all the necessary steps to set up and perform DMA transfers. Design Implementation and PCIe Configuration Lab 5: Implementing the PCIe Design – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode. Root Port Applications Debugging and Compliance Lab 6: Debugging the PCIe Design – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation. Interrupts and Error Management Course Summary

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Experience with PCIe specification protocol
Knowledge of VHDL or Verilog
Some experience with AMD Xilinx implementation tools
Some experience with a simulation tool, preferably the Vivado® simulator
Moderate digital design experience

RELATED COURSES:

Updated 7-14-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.