Versal Adaptive SoC Design Methodologies Workshop

BLT Engineers have successfully deployed designs to Versal devices for Clients. Learn from the experts.

This 4-hour online workshop explores using different AMD Versal™ adaptive SoC design methodologies and techniques for developing designs targeting Versal devices. Also learn about application partitioning, design closure, power, and thermal solutions to enhance the performance of a design.

The emphasis of this course is on:

  • Demonstrating the embedded software development flow for Versal devices
  • Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems
  • Identifying Versal adaptive SoC power and thermal solutions
  • Applying common timing closure techniques
  • Performing system-level simulation and debugging
  • Improving Versal adaptive SoC system performance

This course focuses on the Versal adaptive SoC architecture.


AMD is sponsoring this workshop, with no cost to students. Limited seats available.


Live Online Training (10am-3pm ET)

Training Duration:

1 Day (4 hours)

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Who should attend:

Software and hardware developers, system architects, and anyone who wants to learn about the Versal adaptive SoC design methodologies.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the embedded software development flow for AMD Versal devices
  • Use the provided design tools and Versal adaptive SoC design methodologies to create complex systems
  • Identify Versal adaptive SoC power and thermal solutions
  • Create a custom AMD Vitis platform to run acceleration applications
  • Identify and apply common timing closure techniques
  • Describe the different debugging options available for the Versal adaptive SoC
  • Describe system-level simulation and debugging

Course Outline

Day 1
Board System Design Methodology
Describes PCB, power, clocking, and I/O considerations when designing a system.

Embedded Software Development
Describes the software development environments and embedded software development flows for Versal devices. Also introduces embedded software debugging.

System and Solution Planning Methodology
Describes design partitioning, power, and thermal guidelines. Also reviews system debug, verification, and validation planning.

Hardware, IP, and Platform Development Methodology
Describes the different Versal device design flows and covers the custom platform creation process using the Vivado IP integrator, RTL, HLS, and Vitis environment. 

Timing Closure Overview
Describes the timing closure and baselining of a design. 

System Integration and Validation Methodology
Describes different simulation flows as well as timing and power closure techniques. Also explains how to improve system performance.

DEMO: Hardware, IP, and Platform Development Methodology

Embedded Software Development

DEMO: Debugging

System Simulation

Please note: The instructor may change the content order to provide a better learning experience.


  • Basic knowledge of AMD FPGAs and adaptive SoCs
  • Basic knowledge of the Vivado and Vitis tools


Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.