No Cost - Advanced Debugging Workshop

Advanced Debugging Workshop

This 4-hour workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with general debugging concepts, tools and techniques. Special topics include helping guide attendees through the differences of using ISE Design Suite based ChipScope in Vivado for migrating to 7 Series devices and onward.

Additionally, this workshop will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. The demonstrations utilizing actual AMD ZCU104 Evaluation Boards provide attendees with experience designing, expanding and modifying an embedded system, including techniques for triggering on boot and hardware-software co-debugging.

This workshop is based on BLT’s 1-day class Advanced Debug Techniques for Hardware Engineers.

COST:

AMD is sponsoring this workshop, with no cost to students. Limited seats available.

SCHEDULED CLASSES

Live Online Training (10am-3pm ET)

October 23, 2024

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

1 Day (4 hours)

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Who should attend:

Hardware engineers, system architects, and anyone who wants to learn how to debug challenging issues encountered while developing with FPGAs, SoCs, adaptive SoCs, and PCBs.

Skills Gained

After completing this comprehensive training, you will know how to:

Identify synchronous design techniques
Use the Vivado logic analyzer and debug flows to debug a design
Debugging a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
Debugging a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1
Vivado Debug Methodology Introduction to Vivado Logic Analyzer Debug Cores – Netlist Insertion Flow Debug Cores – HDL Instantiation Flow Introduction to Triggering Transceiver Test and Debugging DEMO: Netlist Insertion Debug Probing Flow DEMO: Adding a Debug Core Using the HDL Instantiation Flow DEMO: IBERT on the ZCU104 Board

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Working HDL knowledge (VHDL or Verilog)
Digital or system design experience

RELATED COURSES:

Updated 12-18-2023

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