No Cost - Advanced Debugging Workshop

Advanced Debugging Workshop

This 4-hour workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado® Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with general debugging concepts, tools and techniques. Special topics include helping guide attendees through the differences of using ISE® Design Suite based ChipScope™ in Vivado® for migrating to 7 Series devices and onward.

Additionally, this workshop will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. The demonstrations utilizing actual Xilinx ZCU104 Evaluation Boards provide attendees with experience designing, expanding and modifying an embedded system, including techniques for triggering on boot and hardware-software co-debugging.

This workshop is based on BLT’s 1-day class Advanced Debug Techniques for Hardware Engineers.

COST:

AMD Xilinx is sponsoring this workshop, with no cost to students. Limited seats available.

SCHEDULED CLASSES

Live Online Training (10am-3pm ET)

December 13, 2023

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

1 Day (4 hours)

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Who should attend:

Hardware engineers, system architects, and anyone who wants to learn how to debug challenging issues encountered while developing with FPGAs, SoCs, ACAPs, and PCBs.

Skills Gained

After completing this comprehensive training, you will know how to:

Identify synchronous design techniques
Use the Vivado™ logic analyzer and debug flows to debug a design
Debugging a design with multiple clock domains with the help of multiple debug cores using the Vivado™ logic analyzer
Debugging a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1
Vivado Debug Methodology Introduction to Vivado Logic Analyzer Debug Cores – Netlist Insertion Flow Debug Cores – HDL Instantiation Flow Introduction to Triggering Transceiver Test and Debugging DEMO: Netlist Insertion Debug Probing Flow DEMO: Adding a Debug Core Using the HDL Instantiation Flow DEMO: IBERT on the ZCU104 Board

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Working HDL knowledge (VHDL or Verilog)
Digital or system design experience

RELATED COURSES:

Updated 7-14-2023

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