Course Calendar
We provide a range of courses including hands-on labs, interactive discussions & best practices to leverage your success. We offer online and in-person training, as well as private training. Our BLT training center is located in Columbia, MD. Class location is noted on the calendar.
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View the calendar below or find a class another way:
COURSE SCHEDULE
Note: Additional courses are available only as private classes. Please see the Course Index for the complete list.
COURSE | CLASS DATE | LOCATION | STATUS |
---|---|---|---|
See All On-Demand Webinars | On-Demand | Recorded | View |
WEBINAR: Maximizing Your Debug with System ILAs | June 26, 2024 @ 2 PM ET | Online | WATCH |
Designing FPGAs Using the Vivado Design Suite 3 - Timing Closure, CDC, and Debugging | November 12-14, 2024 | Live E-Learning | 9 seats left |
Designing with the Zynq UltraScale+ RFSoC | November 12-14, 2024 | Live E-Learning | 5 seats left |
BLT Exclusive: Designing with Verilog | November 19-21, 2024 | Live E-Learning | Closed |
WORKSHOP: Digital Logic 101 | November 20, 2024 @ 10 AM ET | Online | LIMITED SEATS |
WEBINAR: Build Flow for KRIA SOM | November 26, 2024 @ 2 PM ET | Online | LIMITED SEATS |
Designing with VHDL | December 3-5, 2024 | Live E-Learning | 8 seats left |
Dynamic Function eXchange (DFX) Using the Vivado Design Suite | December 3-5, 2024 | Live E-Learning | Closed |
Designing FPGAs Using the Vivado Design Suite 4 – Timing Closure, Floorplanning, Debugging and Tcl | December 10-12, 2024 | Live E-Learning | 9 seats left |
WORKSHOP: From Theory to Practice: Applying Timing Constraints | December 18, 2024 @ 10 AM ET | Online | LIMITED SEATS |
WEBINAR: Understanding AXI | December 19, 2024 @ 2 PM ET | Online | LIMITED SEATS |
BLT Exclusive: Embedded Systems Hardware Design Boot Camp for the Zynq UltraScale+ MPSoC | January 21-23, 2025 | Live E-Learning | 8 seats left |
WORKSHOP: Versal Adaptive SoCs Quick Start Workshop: A Guide to Integration and Implementation | January 22, 2025 @ 10 AM ET | Online | LIMITED SEATS |
Embedded Heterogeneous Design (For Getting Started with Versal Devices) | January 28-30, 2025 | Live E-Learning | Confirmed |
WEBINAR: Optimizing FPGA Designs with Vivado Reports and Design Rule Checks | January 29, 2025 @ 2 PM ET | Online | LIMITED SEATS |
Ultrafast Design Methodology | February 4-6, 2025 | Live E-Learning | Confirmed |
Designing with VHDL | February 11-13, 2025 | Live E-Learning | Confirmed |
Embedded Design with PetaLinux Tools | February 11-13, 2025 | Live E-Learning | 9 seats left |
Designing with Verilog | February 18-20, 2025 | Live E-Learning | Confirmed |
WORKSHOP: Vitis IDE Quick Start | February 19, 2025 @ 10 AM ET | Online | LIMITED SEATS |
Designing FPGAs Using the Vivado Design Suite 1 - FPGA Essentials | March 4-6, 2025 | Live E-Learning | Confirmed |
March 11-13, 2025 | Live E-Learning | Confirmed | |
Vitis Model Composer: A MATLAB and Simulink-based Product (DSP) | March 18-20, 2025 | Live E-Learning | Confirmed |
Designing FPGAs Using the Vivado Design Suite 2– Clocking, IO, IP Integrator | March 25-27, 2025 | Live E-Learning | Confirmed |
BLT Exclusive: Designing and Verification with SystemVerilog | April 8-10, 2025 | Live E-Learning | Confirmed |
Designing FPGAs Using the Vivado Design Suite 3- Timing Closure, CDC, and Debugging | April 29 - May 1, 2025 | Live E-Learning | Confirmed |
Designing with the Zynq UltraScale+ RFSoC | May 13-15, 2025 | Live E-Learning | Confirmed |
May 20-21, 2025 | Live E-Learning | Confirmed | |
Designing FPGAs Using the Vivado Design Suite 4 – Timing Closure, Floorplanning, Debugging and Tcl | June 3-5, 2025 | Live E-Learning | Confirmed |
Operating Systems and Hypervisors in Adaptive SoCs (formerly called ACAPs) | Contact us | Live E-Learning | Contact us |
DSP Design Using System Generator | Contact us | Live E-Learning | Contact us |
Impressed with the effort
Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.
– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization
Thanks for a great class!
I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!
– Student from Vivado Boot Camp for the FPGA User Phase 1
Knowledgeable instructor
Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.
– Student from Designing with VHDL
Can quickly and concisely answer technical questions
I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!
– Student from Vivado Boot Camp for the FPGA User Phase 3
Labs were great
The labs were great and really reinforced the topics.
– Student from Designing with Versal AI Engine 1: Architecture and Design Flow
This one was definitely one of the best
I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!
– Student from Vivado Boot Camp for the FPGA User Phase 1
The instructor was excellent
The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.
– Student from Embedded Design with PetaLinux Tools
I gained a lot of information
The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!
– Student from Vivado Boot Camp for the FPGA User Phase 1
I have a great grasp of HLS and how to use Vitis effectively
I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!
– Student from High-Level Synthesis with the Vitis HLS Tool
I would endorse him to teach a friend
Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.
– Student from Designing with Verilog
Erich was engaging
Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.
– Student from Vivado Boot Camp for the FPGA User Phase 1
Expert tidbits
I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.
– Student from Designing with VHDL
One of the best experiences for AMD Xilinx training that I’ve had
Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.
– Student from Designing with VHDL
My instructor took time
My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.
– Student from Vivado Boot Camp for the FPGA User Phase 3
My instructor was very professional
My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.
– Student from Vivado Boot Camp for the FPGA User Phase 1
College course fit into 3 days
The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.
– Student from Designing with VDHL
Elie was an exceptional instructor
Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.
– Student from Designing with Verilog
I had a wonderful instructor
I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.
– Student from Vivado Boot Camp for the FPGA User Phase 3
All in all a great experience
Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.
– Student from Vivado Boot Camp for the FPGA User Phase 2
My instructor was very capable
My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question
– Student from Vivado Boot Camp for the FPGA User Phase 1
A lot of insights beyond the course
Glenn was a great instructor and provided us with a lot of insights beyond the course material
– Student from Embedded Design with PetaLinux Tools
They had answers for just about every question
Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.
– Student from Vivado Boot Camp for the FPGA User Phase 2