Vitis Model Composer Workshop
Vitis Model Composer Workshop
This 4-hour online workshop provides experience with using the Vitis™ Model Composer tool for model-based designs. This overview workshop is based on our proficiency course, Vitis Model Composer: A MATLAB and Simulink-based Product.
Gain experience with:
- Creating a model-based design using AIE library blocks along with custom blocks in Vitis Model Composer
- Creating Versal® AI Engine graphs and kernels using Vitis Model Composer
- Connecting AI Engine blocks and non-AI Engine blocks
- Verifying and debugging AI Engine code using the Vitis analyzer
- Simulating and debugging a complex system created using AI Engine library blocks
This course focuses on the UltraScale and Versal architectures.
COST:
AMD-Xilinx is sponsoring this workshop, with no cost to students. Limited seats available.
SCHEDULED CLASSES
Training Duration:
1 Day (4 hours)
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Who should attend:
System engineers, system designers, logic designers, and experienced hardware engineers who are implementing Versal AI Engine, HDL, and HLS algorithms using the MathWorks MATLAB® and Simulink® software and want to use Vitis Model Composer.
Skills Gained
After completing this comprehensive training, you will know how to:
- Use optimized AI Engine blocks directly from the Simulink tool library browser
- Create, simulate, and debug a Vitis Model Composer design in the Simulink environment using AIE block libraries
- Perform co-simulation and hardware verification
- Import custom AI Engines code as blocks into Vitis Model Composer
- Generate output products using automatic code generation
- Connect AI Engine blocks and non-AI Engine blocks
- Perform AI Engine code verification using the Vitis analyzer
- Create, simulate, and debug a complex system created using AI Engine library blocks
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Basic experience with the MATLAB and Simulink software
- Basic understanding of DSP designs and sampling theory
- Comfort with the C/C++ programming language for HLS or AI Engine model designs
RELATED COURSES:
- Essential DSP Implementation Techniques for Xilinx FPGAs
- High-Level Synthesis with the Vitis HLS Tool
- Designing with Versal AI Engine 1: Architecture and Design Flow
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
- Designing with Versal AI Engine 3: Kernel Programming and Optimization