OLDER (DEPRECATED) COURSES
The below courses contain older content and are no longer part of our regular course list. They are only offered as a private class.
Please contact our BLT Training Team to find out more.
Deprecated Courses
| Course | Common Topics | Persona | Silicon | Status |
|---|---|---|---|---|
C-based Design: High-Level Synthesis with the Vivado HLx Tool | Vitis, Tools, Testbench, RTL, HLS | Hardware Engineer, Software Engineer, System Architect | FPGA | Deprecated |
| DSP Design Using System Generator | DSP, Tools, Verification, Simulation | Hardware Engineer, System Architect | FPGA | Deprecated |
| BLT Exclusive: Essential DSP Design Techniques using System Generator | DSP, Tools, Verification, Simulation | Hardware Engineer, System Architect | FPGA | Deprecated |
| Designing with the Xilinx 7 Series Families | Architecture, Clocking, DSP | Hardware Engineer, System Architect | FPGA, SoC | Deprecated |
| Developing and Optimizing Applications Using the OpenCL Framework for FPGAs | OpenCL, Debugging, Embedded | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Embedded Systems Design | Embedded, Zynq, Vivado, Tools, Simulation | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Embedded Systems Software Design | Embedded, Zynq, Vivado, Tools, Debugging | Software Engineer | SoC | Deprecated |
| How to Design a High-Speed Memory Interface | Memory, I/O, Debugging, Tools, Testbench | Hardware Engineer | FPGA | Deprecated |
| Migrating to the Vitis Embedded Software Development IDE Workshop | Vitis, Tools, Debugging, Embedded | Hardware Engineer, Software Engineer, System Architect | SoC | Deprecated |
| UltraFast Design Methodology | Vivado, Tools, Timing Constraints, I/O | Hardware Engineer, System Architect | FPGA | Deprecated |
| Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users | Vivado, Tools, Timing Constraints, Tcl | Hardware Engineer | FPGA | Deprecated |
| Vivado Design Suite for ISE Software Project Navigator Users | Vivado, Tools, Simulation, Timing Constraints | Hardware Engineer | FPGA | Deprecated |
| Zynq All Programmable SoC System Architecture | Zynq, Memory, I/O, Architecture | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Advanced Features and Techniques of Embedded Systems Design | Embedded, Vivado, Simulation, Verification | Hardware Engineer, Software Engineer, System Architect | FPGA, SoC | Deprecated |
| Advanced SDSoC Development Environment and Methodology | Architecture, Memory, Vivado, Tools | Hardware Engineer, Software Engineer, System Architect | SoC | Deprecated |
| Designing with Ethernet MAC Controllers | Ethernet, Simulation, Vivado, Testbench, I/O | Hardware Engineer | FPGA | Deprecated |
| Designing with the Spartan-6 and Virtex-6 FPGA Families | Architecture, Spartan-6, Vivado, Tools, Clocking | Hardware Engineer, System Architect | FPGA | Deprecated |
| BLT Exclusive: Designing an Integrated PCI Express System with Xilinx Serial Transceivers | Connectivity, UltraScale+, UltraScale, Clocking, Simulation, Testbench, Debugging, PCIe, Embedded, Signal Integrity | Hardware Engineer, System Architect | FPGA | Deprecated |