Course Description

This course is designed to bring FPGA designers up to speed developing embedded systems using the Vivado Design Suite. The features and capabilities of the Zynq™ UltraScale+® MPSoC and the Zynq™-7000 SoC are covered in lectures, demonstrations and labs, along with general embedded concepts, tools and techniques. Additionally, advanced embedded topics included in this course cover the implementation of level 1 and level 2 device drivers, Asynchronous Multiprocessing (AMP), and Xilinx's embedded operating system, PetaLinux. The hands-on labs utilizing actual Xilinx ZCU104 Evaluation Boards provide students with experience designing, expanding and modifying an embedded system, including booting techniques and hardware-software co-debugging.

Training Duration

Who Should Attend?

Engineers who are interested in developing embedded systems with the Zynq™ UltraScale+® MPSoC and Xilinx Zynq™-7000 SoC using Vivado Design Suite and the Xilinx Software Development Kit (SDK).

Prerequisites

• Basic understanding of programming
• Basic understanding of microprocessors
• Basic understanding of HDLs

Hardware

• Xilinx Zynq™ UltraScale+® MPSoC ZCU104 Evaluation Kit

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Describe the various tools that encompass a Xilinx embedded design
• Rapidly architect an embedded system containing an arm based processor using the Vivado IP integrator and Customization Wizard
• Utilizing the Eclipse-based Software Development Kit (SDK) for embedded software applications
• Create and integrate an IP-based processing system component in the Vivado Design Suite
• Design and add custom AXI interface-based peripherals to an embedded processing system
• Simulate custom AXI interface-based peripherals using the AXI Verification IP

Course Outline

Day 1

1. Course Agenda
2. Embedded UltraFast Design Methodology
3. Overview of Embedded Hardware Development
4. Designing with the IP Integrator
5. LAB: Driving the IP Integrator Tool
6. Introduction to the 7 Series Architecture
7. Introduction to the UltraScale Architecture
8. Introduction to the UltraScale+ Families
9. AXI Introduction
10. AXI Variations
11. AXI Transactions
12. LAB: Building Custom AXI IP
13. Zynq-7000 SoC Architecture Overview
14. Zynq UltraScale+ MPSoC Architectural Overview
15. LAB: Exploring the Architecture of the Zynq UltraScale+ MPSoC
16. Driving the SDK Tool
17. LAB: Driving SDK Tool

Day 2

1. Zynq UltraScale+ MPSoC Clocking
2. Zynq UltraScale+ MPSoC APU Overview
3. Zynq UltraScale+ MPSoC APU Cortex-A53 Processor
4. Zynq UltraScale+ MPSoc RPU Introduction
5. Zynq UltraScale+ MPSoC PMU Introduction
6. Zynq UltraScale+ MPSoC PMU and the IPIs
7. LAB: Managing Power for Other Processors
8. Introduction to Interrupts
9. Hypervisors Introduction
10. ARM TrustZone Technology Overview
11. Zynq UltraScale+ MPSoC DDR
12. AXI DMA
13. Sharing PS Resources (Hardware Perspective)
14. LAB: Sharing PS Resources (Hardware Perspective)
15. LAB: Sharing PS Resources (Software Perspective)
16. Zynq UltraScale+ MPSoC Boot and Configuration
17. Zynq UltraScale+ MPSoC Boot Image
18. FSBL Introduction

Day 3

1. LAB: Loading the PL from Software
2. AXI BFM Simulation Using Verification
3. LAB: Introduction to Verification IP Simulation
4. Hardware-Software Co-Debugging (Cross-Triggering)
5. LAB: Debugging Using Cross-Triggering
6. Understanding Device Drivers
7. LAB: Baremetal Application Development
8. Operating Systems Introduction and Concepts
9. Linux A High-Level Introduction
10. Yocto Relationship with PetaLinux
11. Configuring and Building Linux
12. QEMU Introduction
13. Standalone Software Platform Development
14. Introduction to HLS

Scheduled Classes

Education Investment Options

• To qualify for the Advanced Registration Price,
  full payment must be received 21 days prior to the first day of class.
• Basic follow-on coaching includes 2 hours (max 2 calls)
• Comprehensive follow-on coaching includes 10 hours (max 5 calls).
• Follow-on Coaching must be purchased at time of registration.