Course Description

This course is designed to bring FPGA designers up to speed developing embedded systems using the Vivado Design Suite. The features and capabilities of the Zynq All Programmable System on a Chip (SoC) and the Zynq UltraScale+ MPSoC are covered in lectures, demonstrations and labs, along with general embedded concepts, tools and techniques. The hands-on labs provide students with experience designing, expanding and modifying an embedded system, including booting techniques and hardware-software co-debugging. The last day of class presents everything a hardware engineer would need to know about the Zynq® UltraScale+™ MPSoC family. This latest generation of SoC from Xilinx enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.

Training Duration

Who Should Attend?

Engineers who are interested in developing embedded systems with the Xilinx Zynq™ All Programmable SoC and Zynq UltraScale+ MPSoC using Vivado Design Suite and the Xilinx Software Development Kit (SDK).

Prerequisites

• FPGA design experience
• Basic understanding of programming
• Basic understanding of microprocessors
• Some HDL modeling experience

Hardware

• Zynq-7000 All Programmable SoC ZedBoard

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Describe the various tools that encompass a Xilinx embedded design
• Rapidly architect an embedded system containing an arm based processor using the Vivado IP integrator and Customization Wizard
• Enhance your knowledge of embedded software applications utilizing the Eclipse-based Software Development Kit (SDK)
• Create and integrate an IP-based processing system component in the Vivado Design Suite
• Design and add a custom AXI interface-based peripheral to the embedded processing system
• Simulate a custom AXI interface-based peripheral using the AXI Traffic Generator (ATG)

Course Outline

Day 1

1. Course Agenda
2. Embedded UltraFast Design Methodology
3. Overview of Embedded Hardware Development
4. Driving the IP Integrator Tool
5. Overview of Embedded Software Development
6. Driving the SDK Tool
7. Hardware - Software Flow
8. LAB: Hardware - Software Flow
9. AXI Introduction
10. AXI Variations
11. AXI Transactions
12. AXI Connecting AXI IP
13. AXI Simulation Using Verification
14. LAB: Exploring AXI Transactions Using the AXI Traffic Generator
15. AXI Streaming Introduction
16. AXI Streaming FIFO
17. AXI DMA

Day 2

1. Memory Overview
2. Block RAM Controllers
3. Static Memory Controllers
4. General Interrupt Controller
5. Caching
6. Processor Caching and SCLR
7. Multi-Processor Hardware Architecture
8. Accelerator Coherency Port
9. Zynq-7000 All Programmable SoC Architecture Overview
10. Zynq-7000 AP SoC Dynamic Memory Controller
11. Low-Speed Peripherals Overview
12. Low-Speed Peripherals SPI
13. Low-Speed Peripherals CAN
14. Low-Speed Peripherals I2C
15. Low-Speed Peripherals SD-SDIO
16. Low-Speed Peripherals UART
17. LAB: Exploring the Architecture of the Zynq-7000 All Programmable SoC
18. High-Speed Peripherals USB
19. High-Speed Peripherals Gigabit Ethernet

Day 3

1. Interrupts and the Zynq-7000 Device
2. Zynq-7000 Device PS-PL Interface
3. Sharing PS Resources (Hardware Perspective)
4. LAB: Sharing PS Resources (Hardware Perspective)
5. Debugging Hardware Introduction
6. Hardware-Software Co-Debugging (Cross-Triggering)
7. LAB: Debugging on the Zynq All Programmable SoC
8. Booting Flow
9. Booting PL
10. Booting Flash Image Generation
11. LAB: Loading the PL from Software
12. Zynq UltraScale+ MPSoC Architectural Overview
13. LAB: Exploring the Architecture of the Zynq UltraScale+ MPSoC

 Day 4

1. Zynq UltraScale+ MPSoC APU Overview
2. Zynq UltraScale+ MPSoC APU Cortex-A53 Processor
3. Zynq UltraScale+ MPSoC APU Architecture Extensions
4. Zynq UltraScale+ MPSoC APU 64-Bit Architecture Features
5. Zynq UltraScale+ MPSoC APU Exception Handling
6. Zynq UltraScale+ MPSoC Cache Coherency
7. Hypervisors Introduction
8. Zynq UltraScale+ MPSoC Virtualization Hardware Support
9. Zynq UltraScale+ MPSoC RPU Introduction
10. Zynq UltraScale+ MPSoC RPU L1 and L2 Caches
11. Zynq UltraScale+ MPSoC RPU Clocking, Power and Reset
12. Zynq UltraScale+ MPSoC RPU TCM Architecture
13. Zynq UltraScale+ MPSoC RPU TCM Software
14. Zynq UltraScale+ MPSoC Boot and Configuration
15. Zynq UltraScale+ MPSoC Boot Image
16. Zynq UltraScale+ MPSoC System Memory Management Unit
17. Zynq UltraScale+ MPSoC Peripheral Protection Unit
18. Zynq UltraScale+ MPSoC Memory Protection Unit
19. Zynq UltraScale+ MPSoC Clocking
20. Zynq UltraScale+ MPSoC PS Resets
21. Zynq UltraScale+ MPSoC PMU Introduction
22. Zynq UltraScale+ MPSoC PMU Hardware Architecture
23. Zynq UltraScale+ MPSoC PMU and the IPIs
24. Zynq UltraScale+ MPSoC Power Domains
25. Zynq UltraScale+ MPSoC Power Estimation
26. ARM TrustZone Technology Overview
27. Zynq UltraScale+ MPSoC Security Features
28. QEMU Introduction
29. QEMU Launching

Scheduled Classes

Education Investment Options

• To qualify for the Advanced Registration Price,
  full payment must be received 21 days prior to the first day of class.
• Basic follow-on coaching includes 2 hours (max 2 calls)
• Comprehensive follow-on coaching includes 10 hours (max 5 calls).
• Follow-on Coaching must be purchased at time of registration.