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This course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing and debugging the design. You will also build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system and using proper HDL coding techniques to improve design performance.
Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with Xilinx® FPGAs.
After completing this comprehensive training, you will have the necessary skills to:
Scheduled Sessions | ||
Bottom Line Technologies Training Center - Columbia,MD | 3/26/2019 through 3/28/2019 | REGISTER |
Executive Conference & Training Center - Sterling,VA | 4/2/2019 through 4/4/2019 | REGISTER |
Bottom Line Technologies Training Center - Columbia,MD | 6/11/2019 through 6/13/2019 | REGISTER |
Executive Conference & Training Center - Sterling,VA | 6/18/2019 through 6/20/2019 | REGISTER |
Standard Registration | $2,700 |
Standard Registration | 27 Training Credits |
Advanced Registration **See note below | $2,400 |
Advanced Registration **See note below | 24 Training Credits |
Basic Follow-on Coaching | $499 |
Comprehensive Follow-on Coaching | $2,199 |