Course Description

This course helps in designing an FPGA design, which includes creating a Vivado Design Suite project with source files, simulating the design, performing pin assignments, applying basic timing constraints, synthesizing, implementing and debugging the design. You will also build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system and using proper HDL coding techniques to improve design performance.

Training Duration

Who Should Attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with Xilinx® FPGAs.

Prerequisites

• Vivado® Bootcamp 1
• Designing with VHDL or Designing with Verilog

Hardware

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Use the New Project Wizard to create a new Vivado IDE project
• Describe the supported design flows of the Vivado IDE
• Create a Tcl script to create a project, add sources and implement a design
• Use Tcl scripting in project and non-project batch flows to synthesize, implement and generate custom timing reports
• Synthesize and implement the HDL design
• Use the Schematic and Hierarchy viewers to analyze and cross-probe a design
• Generate a DRC report to detect and fix design issues early in the flow
• Describe and use the clock resources in a design
• Apply clock and I/O timing constraints and perform timing analysis
• Use the Vivado IDE I/O Planning layout to perform pin assignments
• Employ advanced implementation options, such as incremental compile flow, physical optimization techniques and re-entrant mode as last mile strategies
• Use the Vivado IP integrator to create a block design
• Create and package your own IP and add to the Vivado IP catalog to reuse

Course Outline

Day 1

1. Introduction to Vivado Design Flows
2. Introduction to the TCL Environment
3. Lab 1: Introduction to the TCL Environment
4. Vivado Design Suite Project-Based Flow
5. Lab 2: Vivado Design Suite Project-Based Flow
6. Scripting in Vivado Design Suite Project Mode
7. Lab 3: Scripting in Vivado Design Suite Project Mode
8. Vivado Design Suite Non-Project Mode
9. Scripting in Vivado Design Suite Non-Project Mode
10. Lab 4: Scripting in Vivado Design Suite Non-Project Mode
11. Debugging and Error Management in TCL Scripting
12. Introduction to the Xilinx TCL Store
13. Demo: Introduction to the Xilinx TCL Store
14. Behavioral Simulation
15. Synthesis and Implementation
16. Lab 5: Synthesis and Implementation
17. Timing Simulation
18. Lab 6: Timing Simulation
19. Lab 7: Vivado Design Rules Checks

Day 2

1. Design Analysis Using TCL Commands
2. Demo: Design Analysis Using TCL Commands
3. Lab 8: Design Analysis Using TCL Commands
4. Incremental Compile Flow
5. Lab 9: Incremental Compile Flow
6. Physical Optimization
7. Lab 10: Physical Optimization
8. Introduction to Clock Constraints
9. Demo: Introduction to Clock Constraints
10. Lab 11: Introduction to Clock Constraints
11. Timing Constraints Editor
12. Timing Constraints Wizard
13. Lab 12: Timing Constraints Wizard
14. Report Clock Networks
15. Demo: Report Clock Networks
16. Vivado Design Suite I/O Pin Planning
17. Lab 13: Vivado Design Suite I/O Pin Planning
18. I/O Constraints and Virtual Clocks
19. Lab 14: I/O Constraints and Virtual Clocks
20. Demo: Basic Design Analysis in the Vivado IDE
21. Lab 15: Basic Design Analysis in the Vivado IDE

Day 3

1. Setup and Hold Timing Analysis
2. Introduction to Vivado Timing Reports
3. Demo: Introduction to Vivado Timing Reports
4. Timing Summary Report
5. Demo: Timing Summary Report
6. Vivado IP Flow
7. Demo: Vivado IP Flow
8. Lab 16: Vivado IP Flow
9. Creating and Packaging Custom IP
10. Lab 17: Creating and Packaging Custom IP
11. Using an IP Container
12. Demo: Using an IP Container
13. Designing with IP Integrator
14. Demo: Designing with IP Integrator
15. Case Study: Designing with IP Integrator
16. Lab 18: Designing with IP Integrator
17. Managing Remote IP
18. Lab 19: Managing Remote IP

Scheduled Classes

Education Investment Options

• To qualify for the Advanced Registration Price,
  full payment must be received 21 days prior to the first day of class.
• Basic follow-on coaching includes 2 hours (max 2 calls)
• Comprehensive follow-on coaching includes 10 hours (max 5 calls).
• Follow-on Coaching must be purchased at time of registration.