Embedded Systems Hardware Design Boot Camp
Embedded Systems Hardware Design Boot Camp
This course is designed to bring FPGA designers up to speed developing embedded systems using the Vivado™ Design Suite. The features and capabilities of the Zynq® UltraScale+™ MPSoC and the Zynq®-7000 SoC are covered in lectures, demonstrations and labs, along with general embedded concepts, tools and techniques. Additionally, advanced embedded topics included in this course cover the implementation of level 1 and level 2 device drivers, Asynchronous Multiprocessing (AMP), and Xilinx’s embedded operating system, PetaLinux. The hands-on labs utilizing actual Xilinx ZCU104 Evaluation Boards provide students with experience designing, expanding and modifying an embedded system, including booting techniques and hardware-software co-debugging.
This is an advanced class. Those not meeting the prerequisites will struggle.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe the various tools that encompass a Xilinx embedded design
- Rapidly architect an embedded system containing an ARM™ based processor using the Vivado™ IP integrator and Customization Wizard
- Utilizing Vitis for embedded software applications
- Create and integrate an IP-based processing system component in the Vivado™ Design Suite
- Design and add custom AXI interface-based peripherals to an embedded processing system
- Simulate custom AXI interface-based peripherals using the AXI Verification IP
Course Outline
Day 1
- Course Agenda
- Embedded UltraFast® Design Methodology
- Overview of Embedded Hardware Development
- Driving the IP Integrator Tool
- LAB: Driving the IP Integrator Tool
- Introduction to the 7 Series Architecture
- Introduction to the UltraScale™ Architecture
- Introduction to the UltraScale+™ Families
- AXI Introduction
- AXI Variations
- AXI Transactions
- AXI Connecting AXI IP
- LAB: Building Custom AXI IP
- Zynq®-7000 SoC Architecture Overview
- Zynq® UltraScale+™ MPSoC Architectural Overview
- LAB: Exploring the Architecture of the Zynq® UltraScale+™ MPSoC
- Driving the Vitis Tool
- LAB: Driving Vitis Tool
Day 2
- Zynq® UltraScale+™ MPSoC Clocking
- Zynq® UltraScale+™ MPSoC APU Overview
- Zynq® UltraScale+™ MPSoC APU Cortex®-A53 Processor
- Zynq® UltraScale+™ MPSoC RPU Introduction
- Zynq® UltraScale+™ MPSoC RPU TCM Architecture
- Zynq® UltraScale+™ MPSoC PMU Introduction
- Zynq® UltraScale+™ MPSoC PMU and the IPIs
- LAB: Managing Power for Other Processors
- Introduction to Interrupts
- Hypervisors Introduction
- ARM™ TrustZone Technology Overview
- Zynq® UltraScale+™ MPSoC DDR
- Sharing PS Resources (Hardware Perspective)
- LAB: Sharing PS Resources (Hardware Perspective)
- LAB: Sharing PS Resources (Software Perspective)
- Zynq® UltraScale+™ MPSoC Boot and Configuration
- Zynq® UltraScale+™ MPSoC Boot Image
- FSBL Introduction
Day 3
- LAB: Loading the PL from Software
- AXI BFM Simulation Using Verification
- LAB: Introduction to Verification IP Simulation
- Hardware-Software Co-Debugging (Cross-Triggering)
- LAB: Debugging Using Cross-Triggering
- Understanding Device Drivers
- LAB: Standalone Application Development
- Operating Systems Introduction and Concepts
- Linux A High-Level Introduction
- Yocto Relationship with PetaLinux
- Creating a Linux Image and Application Using PetaLinux Tools
- QEMU Introduction
- Standalone Software Platform Development
- Introduction to HLS
Scheduled Classes
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Training Duration:
3 Days
Who should attend:
Engineers who are interested in developing embedded systems with the Zynq® UltraScale+™ MPSoC and Xilinx Zynq®-7000 SoC using Vivado™ Design Suite and Vitis.
Prerequisites:
- Experience using the Vivado™ Design Suite
- Experience using the C programming language
- Experience using VHDL or Verilog
- A basic understanding of microprocessors