Vivado Boot Camp Phase-1: Designing for Performance

This course focuses on understanding as well as how to properly design for the primary resources found in the 7 Series FPGA. Topics covered include device overviews, CLB construction, MMCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, FIFO resources, DSP and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the families (PCI Express technology, analog to digital converters and gigabit transceivers) are also introduced.

This course also introduces the UltraScale and UltraScale+ architectures. Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe all the functionality of the 6-input LUT and the CLB construction of the 7 series and UltraScale FPGAs
  • Specify the CLB resources and the available slice configurations for the 7 series FPGAs
  • Describe the new CLB capabilities of the UltraScale FPGA and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO and DSP resources available for the 7 series and UltraScale FPGAs
  • Describe the UltraRAM features available for the UltraScale FPGAs
  • Properly design for the I/O block and SERDES resources available for the 7 series and UltraScale FPGAs
  • Identify the MMCM, PLL and clock routing resources included with these families
  • Identify the hard resources available for implementing high performance DDR3/DDR4 physical layer interfaces
  • Describe the additional dedicated hardware for all the 7 series family members
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1

  • 7 Series Overview
  • Introduction to UltraScale Architecture
  • CLB Architecture
  • UltraScale Architecture CLB Resources
  • Slice Flip-Flops
  • LAB: CLB Resources
  • LAB: UltraScale Architecture CLB Resources
  • Memory Resources
  • UltraRAM Memory
  • LAB: Memory Resources
  • LAB: UltraRAM Memory
  • DSP Resources

Day 2

  • UltraScale FPGA DSP Resources
  • LAB: DSP Resources
  • I/O Resources
  • LAB: I/O Resources
  • I/O Resources – Component Mode
  • I/O Resources – Native Mode
  • LAB: I/O Resources – Component Mode
  • LAB: I/O Resources – Native Mode
  • Clocking Resources
  • LAB: Clocking Resources

Day 3

  • UltraScale Clocking Resources
  • LAB: UltraScale Architecture Clocking Resources
  • Dedicated Hardware
  • UltraScale Transceivers
  • UltraScale Transceivers Wizard
  • Introduction to UltraScale+ Families
  • LAB: Transceivers Wizard
  • Design Migration Methodology
  • LAB: 10G PCS/PMA and MAC Design Migration
  • Zynq® All Programmable SoC Overview
  • Zynq® UltraScale+ MPSoC: Architectural Overview

Scheduled Classes

Columbia, MD
9/10/2019 – 9/12/2019

Your Facility / A Location near you
10/21/2019 – 10/23/2019

Columbia, MD
2/25/2020 – 2/27/2020

Sterling, Virginia
3/3/2020 – 3/5/2020

Education Investment Options

Standard Registration
$2,700
Standard Registration
27 Training Credits
Advanced Registration
$2,400
Advanced Registration
24 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$2,500

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.

To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

3 Days

Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) who have experience with Xilinx FPGAs.

Prerequisites

  • Working HDL knowledge (VHDL or Verilog)
  • Digital design experience

Version: 2019-10-07_1352