Implementing DSP Using Vitis Model Composer Workshop

This 4-hour online workshop provides experience with using the AMD Vitis Model Composer tool for model-based designs. This overview workshop is based on our proficiency course, Vitis Model Composer: A MATLAB and Simulink-based Product with DSP Techniques.

Gain experience with:

  • Creating a model-based design using AIE library blocks along with custom blocks in Vitis Model Composer
  • Creating Versal AI Engine graphs and kernels using Vitis Model Composer
  • Connecting AI Engine blocks and non-AI Engine blocks
  • Verifying and debugging AI Engine code using the Vitis analyzer
  • Simulating and debugging a complex system created using AI Engine library blocks

This course focuses on the UltraScale and Versal architectures.


AMD is sponsoring this workshop, with no cost to students. Limited seats available.


Live Online Training (10am-3pm ET)

Training Duration:

1 Day (4 hours)

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Who should attend:

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing Versal AI Engine, HDL, and HLS algorithms using the MathWorks MATLAB and Simulink software and want to use Vitis Model Composer.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Use optimized AI Engine blocks directly from the Simulink tool library browser
  • Create, simulate, and debug a Vitis Model Composer design in the Simulink environment using AIE block libraries
  • Perform co-simulation and hardware verification
  • Import custom AI Engines code as blocks into Vitis Model Composer
  • Generate output products using automatic code generation
  • Connect AI Engine blocks and non-AI Engine blocks
  • Perform AI Engine code verification using the Vitis analyzer
  • Create, simulate, and debug a complex system created using AI Engine library blocks

Course Outline

Day 1
  • Introduction to Vitis Model Composer: Introduces the Vitis Model Composer tool and describe the optimized HDL, HLS, and AI Engine library blocks available in Vitis Model Composer.
  • AI Engine Library in Vitis Model Composer: Demonstrates the usage the AI Engine library in Vitis Model composer for creating an AI Engine design, which involves preparing the kernel and importing the AI Engine code as a block.
  • AI Engine Simulation and Code Generation: Illustrates the process of generating AI Engine code with a data flow graph, which involves Simulink simulation with the AI Engine library for functional verification. Also describe the hardware validation flow through generating a hardware image targeting a specific platform for the Simulink environment. {Lecture, Labs}
  • Connecting AI Engine and Non-AI Engine Blocks: Explains how to interconnect AI Engine blocks and non-AI Engine (HDL and HLS) blocks. 
  • Debugging an AI Engine Design in Vitis Model Composer: Shows how to use the Vitis analyzer for viewing and analyzing various parameters that are useful for debugging Versal AI Engines.
  • DEMO: Importing AI Engine Kernels
  • DEMO: Designing with the AI Engine DSP Library and Vitis Model Composer

Please note: The instructor may change the content order to provide a better learning experience.


  • Basic experience with the MATLAB and Simulink software
  • Basic understanding of DSP designs and sampling theory
  • Comfort with the C/C++ programming language for HLS or AI Engine model designs


Updated 12-18-2023
©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.