Designing with Versal AI Engine: Graph Programming with AI Engine Kernels – 2

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Designing with Versal AI Engine: Graph Programming with AI Engine Kernels – 2

Course Code: AIE-GRAPH

This course describes the system design flow and interfaces that can be used for data movement in the Versal AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster development.

In addition, advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade streams, buffer location constraints, runtime parameterization, and APIs to update and read runtime parameters, are covered. The course also highlights how to utilize the Vitis Model Composer tool for AI Engine designs.

The emphasis of this course is on:

  • Implementing a system-level design flow (PS + PL + AIE) and the supported simulation
  • Using an interface for data movement between the PL and AI Engine
  • Utilizing AI Engine APIs for arithmetic operations and advanced MAC intrinsics to implement filters
  • Utilizing the AI Engine DSP library for faster development
  • Applying advanced features for optimizing a system-level design
  • Utilizing the Vitis Model Composer tool for AI Engine designs

Click here for more information about the AMD Versal Adaptive SoC (formerly ACAP).

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
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Scheduled Classes

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Training Duration:

3 Days

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Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

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Who should attend:

Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using our devices.

Software Tools

  • Vitis unified software platform

Hardware

  • Architecture: Versal adaptive SoCs

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
  • Describe the supported emulation for a system-level design
  • Describe the data movement between the PS, PL, and AI Engines
  • Describe the implementation of the AI Engine and programmable logic
  • Implement a system-level design for Versal adaptive SoCs with the Vitis tool flow
  • Describe the Vitis export to Vivado flow
  • Utilize AI Engine APIs, advanced MAC intrinsic syntax, and application-specific intrinsics (such as DDS and FFT)
  • Utilize the AI Engine DSP library for faster development
  • Apply location constraints on kernels and buffers in the AI Engine array
  • Apply runtime parameters to modify application behavior
  • Debug and analyze a system-level design
  • Utilize the AI Engine library in Vitis Model Composer for AI Engine development

Course Outline

Day 1Day 2Day 3

Design Analysis

  • Versal Adaptive SoC: Application Partitioning 1 (Review)
    Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal device. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal adaptive SoC. {Lecture}
  • Versal Adaptive SoC: Application Partitioning 2
    Explains how image and video processing can be targeted for the Versal device by utilizing the different engines (Scalar Engine, Adaptable Engine, and Intelligent Engine). Also describes the AI engine development flow. {Lecture}

Versal AI Engine Data Movement

  • Versal Adaptive SoC: Data Communications 1
    Describes the implementation of AI Engine and programmable logic (PL) kernels and how to implement the functions in the AI Engine that take advantage of low power. {Lecture}
  • Versal Adaptive SoC: Data Communications 2
    Describes the programming model for the implementation of stream interfaces for the AI Engine kernels and PL kernels. Lists the stream data types that are supported by AI Engine and PL kernels. {Lecture, Lab}

Vitis Tool Flow

  • System Design Flow
    Demonstrates the Vitis compiler flow to integrate a compiled AI Engine design graph (libadf.a) with additional kernels implemented in the PL region of the device (including HLS and RTL kernels) and link them for use on a target platform. These compiled hardware functions can then be called from a host program running in the Arm® processor in the Versal device or on an external x86 processor. The Vitis export to Vivado flow is also covered. {Lecture, Labs}

The Programming Model

  • Introduction to AI Engine APIs for Arithmetic Operations
    Describes the Versal AI Engine APIs for arithmetic, comparison, and reduction operations. Also describes the matrix multiplication, FFT, and special multiplication operations. For advanced users, covers how to implement filters using advanced intrinsics functions for various filters, such as non-symmetric FIRs, symmetric FIRs, or half-band decimators. {Lecture}

Libraries

  • AI Engine: DSP Library Overview
    Provides an overview of the available DSP library, which enables faster development and comes with ready-to-use example designs that help with using the library and tools. {Lecture, Labs}

The Programming Model

  • Advanced Graph Input Specifications 1
    Learn advanced features such as using initialization functions, writing directly using streams from the AI Engine, cascade stream, core location constraints, and buffer location constraints. {Lecture}
  • Advanced Graph Input Specifications 2
    Describes how to implement runtime parameterization, which can be used as adaptive feedback and to switch functionality dynamically. {Lecture, Lab}

Debugging

  • Versal AI Engine Application Debug and Trace
    Shows how to debug the AI Engine application running on the Linux OS and how to debug via hardware emulation that allows simulation of the application. {Lecture}

Vitis Model Composer

  • Vitis Model Composer for AI Engine Design
    Describes the Vitis Model Composer tool and how to use the libraries available with the tool for AI Engine design development. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Comfort with the C/C++ programming language
  • Software development flow
  • Vitis software for application acceleration development flow

RELATED COURSES:

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Updated 8-18-2024
©2024 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

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