Designing with Versal™ AI Engine 2: Graph Programming with AI Engine Kernels
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
This course, Versal AI Engine 2, describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster development and advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade stream, buffer location constraints, run-time parameterization and APIs to update and/read run-time parameters.
The emphasis of this course is on implementing a system-level design flow (PS + PL + AIE) and the supported simulation, using an interface for data movement between the PL and AI Engine, utilizing advanced MAC intrinsics to implement filters, utilizing the AI Engine library for faster development, and applying advanced features for optimizing a system-level design.
Click here for more information about the Xilinx Versal ACAP.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
- Describe the supported emulation for a system-level design
- Also describe the data movement between the PS, PL, and AI Engines
- Describe the implementation of the AI Engine and programmable logic
- Implement a system-level design for Versal™ ACAPs with the Vitis™ tool flow
- Utilize advanced MAC intrinsic syntax and application-specific intrinsics such as DDS and FFT
- Utilize the AI Engine DSP library for faster development
- Apply location constraints on kernels and buffers in the AI Engine array
- Apply runtime parameters to modify application behavior
- Debug a system-level design
Course Outline
Day 1
- Application Partitioning on Versal™ ACAPs 1 (Review) {Lecture}
- Application Partitioning on Versal™ ACAPs 2 {Lecture}
- ACAP Data Communications 1 {Lecture}
- ACAP Data Communications 2 {Lecture}
- System Design Flow {Lecture, Lab}
- Introduction to Advanced Intrinsic Functions {Lecture}
Day 2
- Versal™ AI Engine DSP Library Overview {Lecture, Labs}
- Advanced Graph Input Specifications 1 {Lecture}
- Advanced Graph Input Specifications 2 {Lecture, Lab}
- Versal™ AI Engine Application Debug and Trace {Lecture}
Scheduled Classes
Education Investment Options
- To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
- Basic follow-on coaching includes 2 hours (max 2 calls)
- Comprehensive follow-on coaching includes 10 hours (max 5 calls)
- Follow-on Coaching must be purchased at time of registration.
Training Duration:
2 Days
Who should attend:
Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using Xilinx devices
Prerequisites:
- Comfort with the C/C++ programming language
- Software development flow
- Vitis™ software for application acceleration development flow
RELATED COURSES:
- Designing with the Versal™ ACAP: Architecture and Methodology
- Designing with the Versal™ ACAP: Network on Chip
- Designing with Versal™ AI Engine 1: Architecture and Design Flow
- Designing with Versal™ AI Engine 3: Kernel Programming and Optimization
- Designing with the Versal ACAP: Power and Board Design