Designing with the Versal ACAP: Network on Chip

This course introduces the Xilinx Versal ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.

The emphasis of this course is on enumerating the major components comprising the NoC architecture in the Xilinx Versal ACAP, implementing a basic design using the NoC, and configuring the NoC for efficient data movement.

Click here for more information about the Xilinx Versal ACAP.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify the major network on chip components in the Versal ACAP
  • Include the necessary components to access the NoC from the PL
  • Configure connection QoS for efficient data movement

Course Outline

Day 1

  • Architecture Overview for Existing Xilinx Users {Lecture}
  • Versal ACAPs Compared to Zynq® UltraScale+ Devices {Lecture}
  • NoC Introduction and Concepts {Lecture, Lab}
  • NoC Architecture {Lecture}
  • Design Tool Flow Overview {Lecture}
  • NoC DDR Memory Controller {Lecture}
  • NoC Performance Tuning {Lecture, Lab}
  • System Design Migration {Lecture}

Scheduled Classes

Instructor-led Web Based Training

Instructor-led Web Based Training

Instructor-led Web Based Training

Education Investment Options

Standard Registration
Standard Registration
9 Training Credits
Advanced Registration
Advanced Registration
8 Training Credits
Basic Follow-on Coaching
Comprehensive Follow-on Coaching

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.


Versal ACAP Network on Chip


Training Duration:

1 Day

Who should attend:

Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices


  • Any Xilinx device architecture class
  • Familiarity with the Vivado Design Suite


Version: 2021-03-17_0932