Designing with the Versal™ ACAP: Network on Chip
Designing with the Versal ACAP: Network on Chip
This course introduces the Xilinx Versal ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal™ device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on enumerating the major components comprising the NoC architecture in the Xilinx Versal™ ACAP, implementing a basic design using the NoC, and configuring the NoC for efficient data movement.
Click here for more information about the Xilinx Versal ACAP.
|1-Day Instructor-led Course||Price USD||Training Credits|
|Hosted Online - $299/day||$299||3|
|In-Person Registration - $399/day||$399||4|
|Printed Course Book (mailed to you)||$100||1|
|Private Training||Contact Us||Contact Us|
|Follow on Coaching||Contact Us||Contact Us|
Who should attend:
Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal™ ACAP devices
After completing this comprehensive training, you will know how to:
- Identify the major network on chip components in the Versal™ ACAP
- Include the necessary components to access the NoC from the PL
- Configure connection QoS for efficient data movement
Please note: The instructor may change the content order to provide a better learning experience.
- Any Xilinx device architecture class
- Familiarity with the Vivado™ Design Suite
- Designing with the Versal™ ACAP: Architecture and Methodology
- Designing with Versal™ AI Engine 1: Architecture and Design Flow
- Designing with Versal™ AI Engine 2: Graph Programming with AI Engine Kernels
- Designing with Versal™ AI Engine 3: Kernel Programming and Optimization
- Design with the Versal ACAP: Power and Board Design