Designing with the Versal ACAP: Network on Chip

This course introduces the Xilinx Versal ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.

The emphasis of this course is on enumerating the major components comprising the NoC architecture in the Xilinx Versal ACAP, implementing a basic design using the NoC, and configuring the NoC for efficient data movement.

Click here for more information about the Xilinx Versal ACAP.

1-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $299/day$2993
In-Person Registration - $399/day$3994
Printed Course Book (mailed to you)$1001
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Scheduled Classes

Live Online Training:
11/9/2021

Live Online Training:
3/22/2022

Training Duration:

1 Day

We update our schedule regularly. Stay informed.

Who should attend:

Hardware developers and system architects whether migrating from existing Xilinx devices or starting out with the Versal ACAP devices

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify the major network on chip components in the Versal ACAP
  • Include the necessary components to access the NoC from the PL
  • Configure connection QoS for efficient data movement

Course Outline

Day 1
  • Architecture Overview for Existing Xilinx Users {Lecture}
  • Versal ACAPs Compared to Zynq® UltraScale+ Devices {Lecture}
  • NoC Introduction and Concepts {Lecture, Lab}
  • NoC Architecture {Lecture}
  • Design Tool Flow Overview {Lecture}
  • NoC DDR Memory Controller {Lecture}
  • NoC Performance Tuning {Lecture, Lab}
  • System Design Migration {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Updated 9-02-2021