Versal Adaptive SoC: Network on Chip Workshop
Versal Adaptive SoC: Network on Chip Workshop
This workshop introduces the AMD Xilinx® Versal® adaptive SoC network on chip (NoC) to users familiar with AMD Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on enumerating the major components comprising the NoC architecture in the AMD Xilinx Versal adaptive SoC, implementing a basic design using the NoC, and configuring the NoC for efficient data movement.
Click here for more information about the AMD Xilinx Versal Adaptive SoC.
COST:
AMD Xilinx is sponsoring this workshop, with no cost to students. Limited seats available.
SCHEDULED CLASSES
View our Full Calendar for class date status.
(Confirmed, Closed, Full)
Training Duration:
1 Day (4 hours)
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Who should attend:
Hardware developers and system architects whether migrating from existing AMD Xilinx devices or starting out with the Versal adaptive SoC devices.
Skills Gained
After completing this comprehensive training, you will know how to:
- Identify the major network on chip components in the Versal adaptive SoC
- Include the necessary components to access the NoC from the PL
- Configure connection QoS for efficient data movement
Course Outline
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Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Any Xilinx device architecture class
- Familiarity with the Vivado Design Suite
RELATED COURSES:
- Designing with the Versal Adaptive SoC: Architecture and Methodology
- Designing with Versal AI Engine 1: Architecture and Design Flow
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
- Designing with Versal AI Engine 3: Kernel Programming and Optimization
- Design with the Versal Adaptive SoC: Power and Board Design