Designing FPGAs Using the Vivado Design Suite 1

Designing FPGAs Using the Vivado Design Suite 1 – FPGA Essentials

COURSE CODE: FPGA-VDES1

This course offers introductory training on the AMD Vivado Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.

The course provides experience with:

Creating a Vivado project with source files
Simulating a design
Performing pin assignments
Applying basic timing constraints
Synthesizing and implementing
Debugging a design
Generating and downloading a bitstream onto a demo board

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

Live Online Training (9am-5pm ET)

March 4-6, 2025 | Register Today

Training Duration:

3 Days

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

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Who should attend:

Digital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado Design Suite.

Software Tools

Vivado Design Suite

Hardware

Architecture: UltraScale FPGAs
Demo board: Zynq UltraScale+ MPSoC ZCU104 board*

* This course focuses on the UltraScale architecture.

Skills Gained

After completing this comprehensive training, you will know how to:

Use the New Project Wizard to create a new Vivado IDE project
Describe the supported design flows of the Vivado IDE
Generate a DRC report to detect and fix design issues early in the flow
Use the Vivado IDE I/O Planning layout to perform pin assignments
Perform clocking and static timing analysis (STA)
Synthesize and implement an HDL design
Apply clock and I/O timing constraints and perform timing analysis
Use the Xilinx Power Estimator (XPE) tool to estimate power
Use the Schematic and Hierarchy viewers to analyze and crossprobe a design
Use the Vivado logic analyzer and debug cores to debug a design

Course Outline

Day 1	Day 2	Day 3
Device Architectures Introduction to FPGAs Provides an overview of FPGA architecture and describes the advantages, applications, and major building blocks of FPGAs. {Lecture} AMD FPGA and Adaptive SoC Portfolio Introduces 7 series and UltraScale FPGAs, stacked silicon interconnect-based 3D IC devices, Zynq 7000 SoCs, Zynq UltraScale+ MPSoCs, and Versal™ adaptive SoCs. {Lecture} Vivado IDE Overview Introduction to the Vivado Design Suite Describes various design flows and the role of the Vivado IDE in the flows. {Lecture} Introduction to the Tcl Environment Introduces Tcl (tool command language). {Lecture} Vivado Design Suite Project-Based Mode Introduces project-based mode in the Vivado Design Suite, including creating a project, adding files to a project, exploring the Vivado IDE, and simulating a design. {Lecture, Lab} Vivado Design Suite Non-Project Based Mode Describes the design flow using non-project batch mode, including using design analysis commands and how constraints are managed in non-project mode. {Lecture} UltraFast Design Methodology UltraFast Design Methodology: Board and Device Planning Introduces the methodology guidelines on board and device planning. {Lecture} Vivado Tool Flow RTL Development Covers RTL and the RTL design flow, recommended coding guidelines, using control signals, and recommendations on resets. {Lecture} Behavioral Simulation Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture} Vivado IP Flow Demonstrates how to customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo, Lab} Vivado Synthesis and Implementation and Bitstream Generation Reviews creating timing constraints according to the design scenario, synthesizing and implementing the design, and, optionally, generating and downloading a bitstream to a demo board. {Lecture, Lab}	Design Analysis Basic Design Analysis in the Vivado IDE Outlines the various design analysis features in the Vivado Design Suite. {Demo, Lab} Vivado Design Rule Checks Illustrates how to run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations. {Lab} Introduction to Vivado Reports Demonstrates generating and using Vivado timing reports to analyze failed timing paths. {Lecture, Demo} Timing – Basics Introduction to Clock Constraints Shows how to apply clock constraints and perform timing analysis. {Lecture, Demo, Lab} Generated Clocks Demonstrates using the report clock networks report to determine if there are any generated clocks in a design. {Lecture, Demo} I/O Constraints and Virtual Clocks Covers applying I/O constraints and performing timing analysis. {Lecture, Lab} Timing Constraints Wizard Reviews how use the Timing Constraints Wizard to apply missing timing constraints in a design. {Lecture, Lab} Static Timing Analysis (STA) Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture} Setup and Hold Violation Analysis Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}	Pin Planning Vivado Design Suite I/O Pin Planning Describes the I/O Pin Planning layout for performing pin assignments in a design. {Lecture, Lab} Power Power Estimation Using XPE Illustrates estimating the amount of resources and default activity rates for a design and evaluating the estimated power calculated by XPE. {Lecture, Lab} Understanding Design Power Describes the importance of power closure and device selection for better time to market. {Lecture} Versal Adaptive SoC Power Design Manager Discusses using the Power Design Manager tool, including import and export functions. {Lecture} Configuration Introduction to FPGA Configuration Describes how FPGAs can be configured. {Lecture} Debugging Introduction to the Vivado Logic Analyzer Provides an overview of the Vivado logic analyzer for debugging a design. {Lecture, Demo} Introduction to Triggering Introduces the trigger capabilities of the Vivado logic analyzer. {Lecture} Debug Cores Describes how the debug hub core is used to connect debug cores in a design. {Lecture}

Day 1

Day 2

Day 3

Device Architectures

Introduction to FPGAs
Provides an overview of FPGA architecture and describes the advantages, applications, and major building blocks of FPGAs. {Lecture}
AMD FPGA and Adaptive SoC Portfolio
Introduces 7 series and UltraScale FPGAs, stacked silicon interconnect-based 3D IC devices, Zynq 7000 SoCs, Zynq UltraScale+ MPSoCs, and Versal™ adaptive SoCs. {Lecture}

Vivado IDE Overview

Introduction to the Vivado Design Suite
Describes various design flows and the role of the Vivado IDE in the flows. {Lecture}
Introduction to the Tcl Environment
Introduces Tcl (tool command language). {Lecture}
Vivado Design Suite Project-Based Mode
Introduces project-based mode in the Vivado Design Suite, including creating a project, adding files to a project, exploring the Vivado IDE, and simulating a design. {Lecture, Lab}
Vivado Design Suite Non-Project Based Mode
Describes the design flow using non-project batch mode, including using design analysis commands and how constraints are managed in non-project mode. {Lecture}

UltraFast Design Methodology

UltraFast Design Methodology: Board and Device Planning
Introduces the methodology guidelines on board and device planning. {Lecture}

Vivado Tool Flow

RTL Development
Covers RTL and the RTL design flow, recommended coding guidelines, using control signals, and recommendations on resets. {Lecture}
Behavioral Simulation
Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture}
Vivado IP Flow
Demonstrates how to customize IP, instantiate IP, and verify the hierarchy of your design IP. {Lecture, Demo, Lab}
Vivado Synthesis and Implementation and Bitstream Generation
Reviews creating timing constraints according to the design scenario, synthesizing and implementing the design, and, optionally, generating and downloading a bitstream to a demo board. {Lecture, Lab}

Design Analysis

Basic Design Analysis in the Vivado IDE
Outlines the various design analysis features in the Vivado Design Suite. {Demo, Lab}
Vivado Design Rule Checks
Illustrates how to run a DRC report on the elaborated design to detect design issues early in the flow. Fix the DRC violations. {Lab}
Introduction to Vivado Reports
Demonstrates generating and using Vivado timing reports to analyze failed timing paths. {Lecture, Demo}

Timing – Basics

Introduction to Clock Constraints
Shows how to apply clock constraints and perform timing analysis. {Lecture, Demo, Lab}
Generated Clocks
Demonstrates using the report clock networks report to determine if there are any generated clocks in a design. {Lecture, Demo}
I/O Constraints and Virtual Clocks
Covers applying I/O constraints and performing timing analysis. {Lecture, Lab}
Timing Constraints Wizard
Reviews how use the Timing Constraints Wizard to apply missing timing constraints in a design. {Lecture, Lab}
Static Timing Analysis (STA)
Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture}
Setup and Hold Violation Analysis
Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}

Pin Planning

Vivado Design Suite I/O Pin Planning
Describes the I/O Pin Planning layout for performing pin assignments in a design. {Lecture, Lab}

Power

Power Estimation Using XPE
Illustrates estimating the amount of resources and default activity rates for a design and evaluating the estimated power calculated by XPE. {Lecture, Lab}
Understanding Design Power
Describes the importance of power closure and device selection for better time to market. {Lecture}
Versal Adaptive SoC Power Design Manager
Discusses using the Power Design Manager tool, including import and export functions. {Lecture}

Configuration

Introduction to FPGA Configuration
Describes how FPGAs can be configured. {Lecture}

Debugging

Introduction to the Vivado Logic Analyzer
Provides an overview of the Vivado logic analyzer for debugging a design. {Lecture, Demo}
Introduction to Triggering
Introduces the trigger capabilities of the Vivado logic analyzer. {Lecture}
Debug Cores
Describes how the debug hub core is used to connect debug cores in a design. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of the VHDL or Verilog language
Digital design knowledge

RELATED COURSES:

Updated 8-18-2024

©2024 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

Designing FPGAs Using the Vivado Design Suite 1 – FPGA Essentials