Vivado Boot Camp Phase-3: Achieving Performance

This course examines advanced timing constraints and exceptions. It demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, floorplanning and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado Logic Analyzer.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Apply appropriate I/O timing constraints and design modifications for source-synchronous and system-synchronous interfaces
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Describe the "baselining" process to gain timing closure on a design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Apply timing exception constraints in a design as part of the Baselining procedure to fine tune the design
  • Define a properly constrained design
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Utilize floorplanning techniques to improve design performance
  • Use the Vivado logic analyzer and debug flows to debug a design
  • Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
  • Utilize Xilinx security features, bitstream encryption and authentication using AES for design and IP security
  • Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1

  • Generated Clocks
  • Demo: Generated Clocks
  • Clock Group Constraints
  • Demo: Clock Group Constraints
  • Introduction to Timing Exceptions
  • Demo: Introduction to Timing Exceptions
  • LAB: Introduction to Timing Exceptions
  • Timing Constraints Priority
  • I/O Timing Scenarios
  • Source-Synchronous I/O Timing
  • LAB: Source-Synchronous I/O Timing
  • System-Synchronous I/O Timing
  • Demo: System-Synchronous I/O Timing
  • Report Datasheet
  • Demo: Report Datasheet
  • Report Clock Interaction
  • Demo: Report Clock Interaction
  • Case Analysis
  • Baselining
  • Demo: Baselining
  • LAB: Baselining

Day 2

  • Xilinx Power Estimator Spreadsheet
  • LAB: Xilinx Power Estimator Spreadsheet
  • Power Analysis and Optimization Using the Vivado Design Suite
  • LAB: Power Analysis and Optimization Using the Vivado Design Suite
  • Dynamic Power Estimation Using the Vivado Power Report
  • LAB: Dynamic Power Estimation Using the Vivado Power Report
  • Introduction to Floorplanning
  • Design Analysis and Floorplanning
  • LAB: Design Analysis and Floorplanning
  • Revision Control Systems in the Vivado Design Suite
  • LAB: Revision Control Systems in the Vivado Design Suite
  • Introduction to the Vivado Logic Analyzer
  • Demo: Introduction to the Vivado Logic Analyzer
  • Debug Cores
  • HDL Instantiation Flow
  • LAB: HDL Instantiation Flow
  • Netlist Insertion Flow
  • LAB: Netlist Insertion Flow

Day 3

  • Introduction to Triggering
  • Sampling and Capturing Data in Multiple Clock Domains
  • LAB: Sampling and Capturing Data in Multiple Clock Domains
  • Debug Flow in an IP Integrator Design
  • LAB: Debug Flow in an IP Integrator Design
  • Remote Debugging Using the Vivado Logic Analyzer
  • LAB: Remote Debugging Using the Vivado Logic Analyzer
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
  • LAB: Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
  • Trigger and Debug at Device Startup
  • Demo: Trigger and Debug at Device Startup
  • Scripting for a VLA Design
  • LAB: Scripting for a VLA Design
  • Vivado Design Suite ECO Flow
  • LAB: Vivado Design Suite ECO Flow
  • Bitstream Security
  • LAB: Bitstream Security
  • Vivado Design Suite Debug Methodology

Scheduled Classes

Columbia, MD
7/16/2019 - 7/18/2019
Sterling, Virginia
7/23/2019 - 7/25/2019
Trevose, PA
10/15/2019 - 10/17/2019
Parsippany, NJ
10/15/2019 - 10/17/2019
Rochester, NY
10/22/2019 - 10/24/2019
Hauppauge, NY
10/29/2019 - 10/31/2019
Sterling, Virginia
11/5/2019 - 11/7/2019
Columbia, MD
11/12/2019 - 11/14/2019

Education Investment Options

Standard Registration
$2,700
Standard Registration
27 Training Credits
Advanced Registration
$2,400
Advanced Registration
24 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$800
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

3 Days

Who should attend:

Experienced Xilinx FPGA designers

Prerequisites

FPGA design experience

Vivado Bootcamp 2

Working VHDL or Verilog knowledge and experience

Software Tools

Vivado Design or System Edition 2018.1

Hardware

Architecture: Ultrascale and 7 series FPGAs*Demo board (optional): Kintex Ultrascale FPGA KCU105 board or Kintex-7 FPGA KC705 board** This course focuses on the Ultrascale and 7 series architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Last Updated: 2019-06-06_1626