![HLS Patch for Vitis and Vivado](https://bltinc.com/wp-content/uploads/2022/01/BLT_blogPost_HLS-Patch_1200x628-2022-01-12-1024x536.jpg)
HLS Patch for Vitis and Vivado
Xilinx releases HLS Patch to Fix Export Error If you use HLS in the Xilinx® Vitis™ and/or Vivado® tools, you may have encountered an export error. The error began on January 1, 2022. This applies to designs for Versal® ACAPs, Zynq® UltraScale+ MPSoCs and other devices that use high-level synthesis. This new error causes the … Continued