HLS Patch for Vitis and Vivado

Xilinx releases HLS Patch to Fix Export Error

If you use HLS in the Xilinx® Vitis™ and/or Vivado® tools, you may have encountered an export error. The error began on January 1, 2022. This applies to designs for Versal® ACAPs, Zynq® UltraScale+ MPSoCs and other devices that use high-level synthesis.

This new error causes the export_ip command to fail to export the ip.

Per Xilinx, “Vivado and Vitis tools that use HLS in the background are also affected by this issue. HLS tools set the ip_version in the format YYMMDDHHMM and this value is accessed as a signed integer (32-bit) that causes an overflow and generates the errors below (or something similar). Xilinx recommends that all customers apply this patch to be on the safe side.”

Xilinx released an HLS patch, Patch y2k22_patch-1.2, to remedy the issue. The patch is located at the very bottom of this page: Export IP Invalid Argument / Revision Number Overflow Issue (Y2K22) (xilinx.com)

Additional information about the error and instructions on how to install the patch are also located on that page.