BLT Webinars and Workshops Schedule

BLT offers a no-cost series of webinars and workshops on topics ranging from Versal designs to managing FPGA projects and everything in between. Each event in the series includes live instruction with Q&A with a BLT expert. Workshops are sponsored by AMD.

What’s the difference between a webinar and a workshop?

Webinars are 30 minutes to an hour long, and usually include one demo and a Q&A session with our topic expert. Webinars are available on-demand after the event.

Workshops are 6 hours long and include questions throughout and several demos. Workshops are not available on-demand.

Both event types include recordings sent to attendees after the event.

Sign up to hear about upcoming webinars:

Complete List of Upcoming No-Cost Events

COURSEEVENT DATELENGTHLOCATIONSTATUS
Recordings of previous webinars are located in the table below this one.
WEBINAR: Advanced Triggering with Trigger State MachinesOnline1 HourOn-DemandWatch
WORKSHOP: Migrating from UltraScale+ Devices to Versal Adaptive SoCs (Sponsored by AMD)March 19, 20251 DayOnlineRegister
WEBINAR: QEMU Simplified: Building and Debugging Linux Applications with PetaLinuxMarch 26, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Intro to Vitis Model Composer: Accelerating Your Design Workflow (Sponsored by AMD)April 23, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Design Smarter: I/O Pin Planning Best Practices with AMD VivadoApril 30, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Debugging Techniques for Vivado Block Designs Including IP Integrator Workshop (Sponsored by AMD)May 21, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Achieve Faster and Secure DFX Implementations with Versal Abstract ShellsMay 28, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Digital Logic 101 (Sponsored by AMD)June 24, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Integrating HLS Modules into Block DesignsJune 26, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Vivado Quick Start with Versal Devices (Sponsored by AMD)July 23, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Basic Booting for AMD Zynq and Versal Devices with Practical Tips and TechniquesJuly 30, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Designing DSP Applications with Versal AI Engines (Sponsored by AMD)August 20, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Maximizing RFSoC Potential with Functionality and ConfigurabilityAugust 27, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Accelerating Connectivity with the Versal Adaptive SOC Network on Chip (Sponsored by AMD)September 17, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Getting Started with the Vitis Unified IDESeptember 24, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Achieving Timing Closure in FPGA Designs (Sponsored by AMD)October 22, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN AccelerationOctober 29, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: From Theory to Practice: Applying Timing Constraints (Sponsored by AMD)November 19, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Mastering Clock Domain Crossings (CDC) and Synchronization TechniquesNovember 25, 2025 @ 2 PM ET1 HourOnlineRegister
WORKSHOP: Essential Debugging Techniques (Sponsored by AMD)December 17, 2025 @ 10 AM ET1 DayOnlineRegister
WEBINAR: Building Web-Enabled Applications with Embedded LinuxDecember 18, 2025 @ 2 PM ET1 HourOnlineRegister

Complete List of Webinar Recordings

Missed registering for a webinar and the on-demand isn’t ready yet? Email [email protected].

COURSEEVENT DATELOCATIONSTATUS
Webinar: Advanced Triggering with Trigger State MachinesOn-DemandRecordedVideo Coming Soon
Webinar: Optimizing FPGA Designs with Vivado Reports and Design Rule ChecksOn-DemandRecordedWatch
Webinar: Understanding AXI: Streamlining Data Flow and System IntegrationOn-DemandRecordedWatch
Webinar: Build Flow for KRIA SOMOn-DemandRecordedWatch
Webinar: Enhancing System Reliability with the AMD Isolation Design Flow and Dynamic Function ExchangeOn-DemandRecordedWatch
Webinar: Advanced RFSoC Analysis with AMD: Leveraging the RF Analyzer Tool for In-Depth InsightsOn-DemandRecordedWatch
Webinar: Increasing Design Performance Using QoR ReportsOn-DemandRecordedWatch
Webinar: What Is AMD AI Inference? Optimizing Model Deployment for Real-World ApplicationsOn-DemandRecordedWatch
Webinar: Maximizing Your Debug with System ILAsOn-DemandRecordedWatch
Webinar: What Is the AI Engine?On-DemandRecordedWatch
Webinar: Versal AI Engine Tool Flow Explained: Enhancing Your Development JourneyOn-DemandRecordedWatch
Webinar: Demystifying Clock Domain Crossings (CDC) and Synchronization CircuitsOn-DemandRecordedWatch
Webinar: Debug Techniques for Vivado Block DesignsOn-DemandRecordedWatch
Webinar: Closing Timing Using Intelligent Design Runs (Spotlight on New AMD Tool Feature)On-DemandRecordedWatch
Webinar: Introduction to AXI: What Is AXI?On-DemandRecordedWatch
Webinar: Techniques for Space Applications - Including RFSoCs, Ruggedized Devices and Safe State MachinesOn-DemandRecordedWatch
Webinar: Getting Started with the Kria SOMOn-DemandRecordedWatch
Webinar: Understanding Verification for Digital DesignOn-DemandRecordedWatch
Webinar: Dark Mode in Vitis: The New IDEOn-DemandRecordedWatch
Webinar: HLS: What Is It and When Do You Use It?On-DemandRecordedWatch
Webinar: Engineering Roundtable: Verification of SoC DesignsOn-DemandRecordedWatch
Webinar: BLT Engineering Roundtable - Design Productivity Tricks for Busy EngineersOn-DemandRecordedWatch
Webinar: Debugging Using Cross TriggeringOn-DemandRecordedWatch
Webinar: Accelerating AI with the Vitis Unified Software PlatformOn-DemandRecordedWatch
Webinar: Xilinx for ManagersOn-DemandRecordedWatch
Webinar: Interfacing DDR with Programmable Logic on the Versal NoCOn-DemandRecordedWatch