Engineering Roundtable: Verification of SoC Designs – On-Demand Webinar

On-Demand Webinar

Do you need to better understand Verification for your designs? Join us for a 1-hour webinar to look at where and when to use randomization, explore stimulus generation and auto checking, and learn about SystemVerilog randomization. This webinar will include live demos and a Q&A session with our BLT verification expert.

BLT (Bottom Line Technologies), an AMD Authorized Training Provider and Premier Partner, presents this webinar.

To view the on-demand recording from our Engineering Roundtable: Verification of SoC Designs Webinar, please complete the form below. The link will be emailed to you.