Designing with the Versal Adaptive SoC: PCI Express Systems

Home > AMD Training Courses > Connectivity Courses > Designing with the Versal Adaptive SoC: PCI Express Systems

Designing with the Versal Adaptive SoC: PCI Express Systems

COURSE CODE: ACAP-PCIE

This course introduces the features and capabilities of the PCIe and Cache Coherent Interconnect blocks in the AMD Versal adaptive SoC architecture. Learn how to implement a Versal device PCI Express solution in custom applications to improve time to market.

The emphasis of this course is on:

  • Describing the PCI Express design methodology for Versal devices
  • Reviewing various Versal device PCI Express core products
  • Selecting the PCI Express IP cores from the Vivado Design Suite
  • Generating PCI Express example designs and simple applications
  • Identifying the advanced capabilities of the PCIe specification

This course also focuses on the AXI-Streaming interconnect.

Learn more about PCI Express and AMD Technology.

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

3 Days

REGISTER

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Be the first to know. Sign up for our newsletter.

SIGN UP

Who should attend:

  • Hardware designers who want to create applications using Versal device IP cores for PCI Express
  • Software engineers who want a deeper understanding of the Versal device PCI Express solutions
  • System architects who want to leverage key Versal device advantages related to performance, latency, and bandwidth in PCI Express applications

Software Tools

  • Vivado Design Suite

Hardware

  • Architecture: Versal adaptive SoC

Skills Gained

After completing this comprehensive training, you will know how to:

  • Construct a basic PCI Express system by:
    • Selecting the appropriate IP for your application
    • Specifying the requirements of an endpoint application
    • Connecting PCIe IPs with the user application
    • Utilizing PL and PS resources supporting PCI Express
    • Simulating and implementing PCI Express systems
  • Identify the advanced capabilities of the PCI Express specification protocol and feature set

Course Outline

Day 1Day 2Day 3
Introduction to PCI Express
Introduces the course and discusses a few key topics of the PCI Express protocol. {Lecture, Lab}

Versal Adaptive SoC PCIe Solutions
Overview Provides an overview of the PCI Express solutions in the Versal architecture and identifies key differentiators. {Lecture}

PCIe Block Architecture and Functionality
Describes the PL PCIe block architecture. You will learn details on the block features and functionality. {Lecture}

PCIe Block Interfaces Overview
Provides an overview of the PL PCIe block interfaces. Deeper discussion on physical layer and general interfaces. {Lecture}

PCIe Block Requester Interfaces
Reviews the requester AXI4-Streaming core interfaces. You will learn how to utilize packet descriptors for request interfaces. {Lecture}

PCIe Block Completer Interfaces
Reviews the completer AXI4-Streaming core interfaces. You will learn how to utilize packet descriptors for completion interfaces. {Lecture, Lab}

PHY for PCI Express
Describes the Versal device PHY for PCI Express IP architecture and interfaces. You will learn how to utilize this soft IP in PCI Express designs. {Lecture}		PCIe Block Customization
Illustrates customizing the PL PCIe block. You will learn how to utilize the various configuration options. {Lecture, Lab}

PCIe Block Test Bench and Simulation
Discusses PCIe block simulation. You will learn how to utilize the generated example design to verify the functionality of the PL PCIe solution. {Lecture, Lab}

PCIe Block Implementation
Discusses implementation topics. You will review the placement recommendations for the PL PCIe blocks, transceivers, clocks, and resets. {Lecture, Lab}

PL PCIe Block Debugging Overview
Describes the PCI Express debugging options in the Versal device PCI Express physical and transaction layers. You will learn how to perform PCI Express link debug. {Lecture, Lab}

CPM Architecture and Functionality
Describes the CPM block architecture and functionality. You will learn the commonalities and differences to the PL PCIe solution. {Lecture}		CPM Block Customization
Reviews the configuration options of the CIPS CPM block. You will learn how to customize the CPM PCIe block. {Lecture}

CPM IP Use Cases
Describes typical use cases for the Versal device PCI Express solutions to enable you to select the right solution for your design requirements. {Lecture, Lab}

Introduction to DMA
Reviews DMA basics and describes DMA in the context of the PCI Express standard. {Lecture}

PL PCIe XDMA/Bridge Subsystem
Describes the Versal device XDMA architecture and features as well as DMA descriptor usage and interface options. You will learn how to utilize the XDMA subsystem. {Lecture, Lab}

PL PCIe QDMA Subsystem
Describes the Versal device QDMA architecture and features. You will learn how to utilize the QDMA subsystem and its queue usage. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Experience with the PCI/PCIe specification protocol
  • Experience with the Vivado Design Suite
  • Moderate digital design experience

RELATED COURSES:

REGISTER
Updated 12-26-2024
©2024 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

©2024 BLT Inc. All Rights Reserved.

∧