Designing with Versal AI Engine: Architecture and Design Flow – 1

Versal Adaptive SoC Architecture

• Overview of the AMD Versal Adaptive SoC Architecture
  Provides an overview of the Versal architecture at a high level and describes the various engines in the Versal device, such as the Scalar Engines, Adaptable Engines, and Intelligent Engines. Also describes how the AI Engine in the Versal device meets many dynamic market needs. {Lecture}

Versal AI Engine Architecture

• Versal AI Engine Architecture
  Introduces the architecture of the AI Engine and its components. {Lecture}
• AI Engine Interfaces
  Describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces. {Lecture}
• Versal AI Engine Memory and Data Movement
  Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays. {Lecture}

Vitis Tool Flow

• Versal AI Engine Tool Flow
  Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Labs}

Design Analysis

• Versal Adaptive SoC: Application Partitioning 1
  Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal device. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal adaptive SoC. {Lecture}

The Programming Model

• Scalar and Vector Data Types
  Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. {Lecture}
• AI Engine APIs
  Describes what AI Engine APIs are, the three types of vector manipulation operations using AI Engine APIs (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions. {Lecture}

Design Analysis

• Vitis Analyzer
  Describes the different reports generated by the tool and how to view the reports that help to optimize and debug AI Engine kernels using the Vitis analyzer tool. {Lecture}

The Programming Model

• Windows, Buffers, and Streaming Data APIs
  Describes window, i/o buffers and streaming data APIs and reviews the various buffer operations for kernels. {Lecture}
• The Programming Model: Single Kernel
  Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program using the Vitis IDE tool. {Lecture, Lab}

• The Programming Model: Single Kernel Using Vector Data Types
  Illustrates Versal AI Engine kernel programming in detail, reviewing the scalar kernel code and comparing with vector kernel code that utilizes AI Engine APIs and vector data types. {Lab}
• The Programming Model: Introduction to the Adaptive Data Flow (ADF) Graph
  Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports. {Lecture}
• The Programming Model: Multiple Kernels Using Graphs
  Describes the ADF graph in detail and demonstrates the steps to create a graph and set the runtime ratio and graph control APIs from the main application program. {Lecture, Lab}