Designing with the Versal ACAP: Architecture and Methodology

This course helps you to learn about Xilinx Versal ACAP architecture and design methodology.

The emphasis of this course is on reviewing the architecture of the Versal ACAP, describing the different engines available in the Versal architecture and what resources they contain, utilizing the hardened blocks available in the Versal architecture, using the design tools and methodology provided by Xilinx to create complex systems, describing the network on chip (NoC) and AI Engine concepts and their architectures, and performing system-level simulation and debugging.

Click here for more information about the Xilinx Versal ACAP.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe the Versal ACAP architecture at a high level
  • Describe the various engines in the Versal ACP device
  • Use the various blocks from the Versal architecture to create complex systems
  • Perform system-level simulation and debugging
  • Identify and apply different design methodologies

Course Outline

Day 1

  • Introduction {Lecture}
  • Architecture Overview {Lecture}
  • Design Tool Flow {Lecture, Lab}
  • Adaptable Engines (PL) {Lecture}
  • Processing System {Lecture}
  • PMC and Boot and Configuration {Lecture, Lab}
  • SelectIO Resources {Lecture}
  • Clocking Architecture {Lecture, Lab}
  • System Interrupts {Lecture}

Day 2

  • Timers, Counters, and RTC {Lecture}
  • Software Build Flow {Lecture, Lab}
  • Software Stack {Lecture}
  • DSP Engine {Lecture}
  • AI Engine {Lecture}
  • NoC Introduction and Concepts {Lecture, Lab}
  • Device Memory {Lecture}
  • Programming Interfaces {Lecture}
  • Application Partitioning {Lecture}

Day 3

  • PCI Express & CCIX {Lecture, Lab}
  • Serial Transceivers {Lecture}
  • Power and Thermal Solutions {Lecture}
  • Debugging {Lecture, Lab}
  • Security Features {Lecture}
  • System Simulation {Lecture, Lab}
  • System Design Methodology {Lecture}

Scheduled Classes

Instructor-led Web Based Training
3/23/2021 – 3/25/2021

Instructor-led Web Based Training
4/20/2021 – 4/22/2021

Education Investment Options

Standard Registration
$2,700
Standard Registration
27 Training Credits
Advanced Registration
$2,400
Advanced Registration
24 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$2,500

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.

 

Designing with the Versal ACAP: Architecture and Methodology

REGISTER

Training Duration:

3 Days

Who should attend:

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Xilinx Versal ACAP device

Prerequisites:

  • Comfort with the C/C++ programming language
  • Vitis IDE software development flow
  • Hardware development flow with the Vivado Design Suite
  • Basic knowledge of UltraScale/UltraScale+ FPGAs and Zynq® UltraScale+ MPSoCs

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