FPGA Design Closure Techniques

Design Closure Techniques

COURSE CODE: FPGA-DSGNCLOSURE

This is an intermediate course. If you are new to AMD FPGAs, start here.

Learn how to achieve design closure more efficiently and productively with AMD FPGAs and SoCs by using the three pillars of design closure (functional closure, timing closure, and power closure). Also learn how to solve functional behavior, timing, and power simultaneously to achieve faster time-to-market results.

The emphasis of this course is on:

Defining what design closure is and describing the three pillars of design closure (functional closure, timing closure, and power closure)
Using recommended coding techniques
Creating a test bench for functional verification
Applying initial design checks and reviewing timing summary and methodology reports for a design
Using baselining to verify that a design meets timing goals and applying the guidelines described in the baselining process
Performing quality of results (QoR) assessments at different stages to improve the QoR score
Implementing Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1200	12
In-Person Public Registration - $600/day	$1200	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

Live Online Training (9am-5pm ET)

May 20-21, 2025 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

2 Days

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Be the first to know. Sign up for our newsletter.

Who should attend:

Software and hardware developers, system architects, and anyone who wants to learn about design closure techniques related to functional and timing closure.

Software Tools

Vivado Design Suite

Hardware

Architecture: UltraScale FPGAs and Versal adaptive SoCs

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe what is design closure is as well as its three pillars
Create a test bench for functional verification
Resolve setup and hold violations by reducing logic delay and net delay
Improve clock skew and clock uncertainty
Identify clock domain crossings (CDC) and scenarios that require synchronization circuits
Perform QoR assessment at different stages and improve the QoR score
Implement Intelligent Design Runs (IDR)

Course Outline

Day 1	Day 2
Introduction Introduction to Design Closure: Defines what design closure is and identifies the three pillars of design closure. {Lecture} Functional Closure HDL Coding Techniques: Covers basic digital coding guidelines used in an FPGA design. {Lecture} Creating a Test Bench: Describes the design components of a test bench, the different test bench types and how a self-checking test bench can be constructed. {Lecture} Behavioral Simulation: Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture} Timing Simulation: Simulate the design post-implementation to verify that a design works properly on hardware. {Lecture, Lab} Timing Closure Introduction to Clocking and Static Timing Analysis (STA): Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture} Introduction to UltraFast Design Methodology Timing Closure: Provides an overview of the various stages of the UltraFast Design Methodology for timing closure. {Lecture} Baselining: Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing. {Lecture, Lab} Setup and Hold Violation Analysis: Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture} Reducing Logic Delay: Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture}	Timing Closure (continued) Reducing Net Delay: Reviews different techniques to reduce congestion and net delay. {Lecture, Lab} Improving Clock Skew: Describes how to apply various techniques to improve clock skew. {Lecture} Improving Clock Uncertainty: Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab} Clock Domain Crossing (CDC) and Synchronization Circuits: Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits. {Lecture, Lab} QoR Reports Overview: Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture, Lab} Intelligent Design Runs (IDR): Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}

Day 1

Day 2

Introduction

Introduction to Design Closure: Defines what design closure is and identifies the three pillars of design closure. {Lecture}

Functional Closure

HDL Coding Techniques: Covers basic digital coding guidelines used in an FPGA design. {Lecture}

Creating a Test Bench: Describes the design components of a test bench, the different test bench types and how a self-checking test bench can be constructed. {Lecture}

Behavioral Simulation: Describes the process of behavioral simulation and the simulation options available in the Vivado IDE. {Lecture}

Timing Simulation: Simulate the design post-implementation to verify that a design works properly on hardware. {Lecture, Lab}

Timing Closure

Introduction to Clocking and Static Timing Analysis (STA): Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). {Lecture}

Introduction to UltraFast Design Methodology Timing Closure: Provides an overview of the various stages of the UltraFast Design Methodology for timing closure. {Lecture}

Baselining: Demonstrates the performance baselining process, which is an iterative approach to incrementally constrain a design and meet timing. {Lecture, Lab}

Setup and Hold Violation Analysis: Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. {Lecture}

Reducing Logic Delay: Describes how to optimize regular fabric paths and paths with dedicated blocks and macro primitives. {Lecture}

Timing Closure (continued)

Reducing Net Delay: Reviews different techniques to reduce congestion and net delay. {Lecture, Lab}

Improving Clock Skew: Describes how to apply various techniques to improve clock skew. {Lecture}
Improving Clock Uncertainty: Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab}

Clock Domain Crossing (CDC) and Synchronization Circuits: Explains what clock domain crossings (CDC) are and the scenarios that require synchronization circuits. {Lecture, Lab}

QoR Reports Overview: Describes what quality of result (QoR) is and how to analyze the QoR reports generated by the Vivado IDE. {Lecture, Lab}

Intelligent Design Runs (IDR): Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of FPGA and SoC architecture and HDL coding techniques
Basic knowledge of the Vivado Design Suite

RELATED COURSES:

Updated 8-18-2024

©2024 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.