Accelerating Applications with the Vitis Unified Software Environment

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Accelerating Applications with the Vitis Unified Software Environment

COURSE CODE: AI-ACCEL

Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis unified software environment targeting both data center and embedded applications.

The emphasis of this course is on:

  • Using OpenCL APIs to run hardware kernels on Alveo accelerator cards
  • Scheduling hardware kernels and controlling data movement by using OpenCL APIs and the Xilinx Runtime library for embedded platforms
  • Demonstrating the Vitis environment GUI flow and makefile flow for both data center and embedded applications
  • Describing the Vitis platform execution model and XRT
  • Describing kernel development using C/C++ and RTL
  • Analyzing reports with the Vitis analyzer tool
  • Optimizing designs

Learn more about the AMD Vitis Unified IDE.

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
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CoachingLearn MoreLearn More

Scheduled Classes

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View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

3 Days

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Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

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Who should attend:

Anyone needing to accelerate software applications using FPGAs and adaptive SoCs (such as Zynq 7000, Zynq UltraScale+, and Versal devices).

Software Tools

  • Vitis unified software environment

Hardware

  • Architecture: Alveo accelerator cards, SoCs, and adaptive SoCs
  • Demo board: Zynq UltraScale+ MPSoC ZCU104 board

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe how the FPGA architecture lends itself to parallel computing
  • Explain how the Vitis unified software environment helps software developers to focus on applications
  • Describe the Vitis (OpenCL API) execution model and XRT native APIs
  • Analyze the OpenCL API memory model
  • Create kernels from C, C++, or RTL IP using the RTL Kernel Wizard
  • Apply host code optimization and kernel optimization techniques
  • Move data efficiently between kernel and global memory

Course Outline

Day 1Day 2Day 3
Vitis Tool Flow
  • Introduction to the Vitis Unified Software Platform
    Explains how software/hardware engineers and application developers can benefit from the Vitis unified software environment and OpenCL framework. {Lecture}
  • Amdahl's Law
    Provides insights into selecting functions for acceleration by illustrating its impact on system performance. {Lecture, Lab}
  • Vitis Unified Software Platform
    Overview for Accelerator Development Describes the elements of the development flow, such as software emulation, hardware emulation, and system run as well as debugging support for the host code and kernel code. {Lecture, Labs}
  • Vitis Command Line Flow
    Introduces the Vitis environment makefile flow where the user manages the compilation of host code and kernels. {Lecture, Labs}

Basics of Hardware Acceleration
  • Introduction to Hardware Acceleration
    Outlines the fundamental aspects of FPGAs, SoCs, and ACAPs that are required to guide the Vitis tool to the best computational architecture for any algorithm. {Lecture}

Alveo Data Center Accelerator Cards
  • Alveo Data Center Accelerator Cards
    Overview Describes the Alveo Data Center accelerator cards and lists the advantages of these cards and the available software solutions stack. {Lecture}
  • Getting Started with Alveo Data Center Accelerator Cards
    Describes the hardware and software installation procedures for the Alveo Data Center accelerator cards. {Lecture}
Vitis Execution Model and XRT
  • Vitis Execution Model and XRT
    Describes the XRT and the OpenCL APIs used for setting up the platform, executing the target device, and post-processing. {Lecture, Lab}
  • Xilinx Runtime Library (XRT) Native APIs
    Describes the XRT native APIs used for opening a device, loading XCLBIN, creating buffers, executing a kernel, and controlling a graph. {Lecture, Lab}
  • Synchronization
    Describes OpenCL synchronization techniques such as events, barriers, blocking write/read, and the benefit of using out-of-order execution. {Lecture, Lab}
  • Xilinx Card Utilities
    Describes the various tool utilities available with the Xilinx Runtime (XRT), such as board, board management, and XCLBIN utilities. The various commands and usage of these utilities are also covered. {Lecture}

NDRanges (Optional)
  • Introduction to NDRanges
    Explains the basics of NDRange (N dimensional range) and the OpenCL execution model that defines how kernels execute with the NDRange definition. {Lecture}
  • Working with NDRanges
    Outlines the host code and kernel code changes with respect to NDRange. Also explains how NDRange works and the best way to represent the work-group size for the FPGA architecture. {Lecture}

Design Analysis
  • Profiling
    Describes the different reports generated by the tool and how to view the reports that help to optimize data transfer and kernel optimization using the Vitis analyzer tool. {Lecture}
  • Debugging
    Explains the support for debugging host code and kernel code as well as tips to debug the system. {Lecture}

Kernel Development
  • Introduction to C/C++ based Kernels
    Describes the trade-offs between C/C++, OpenCL, and RTL applications and the benefits of C-based kernels. {Lecture, Lab}
Kernel Development
  • Using the RTL Kernel Wizard to Reuse Existing IP as Accelerators
    Describes how the Vitis unified software development provides RTL kernel developers with a framework to integrate their hardware functions into an application running on a host PC connected to an FPGA via a PCIe interface. {Lecture, Lab}

Optimization Methodology Guide
  • Optimization Methodology
    Describes the recommended flow for optimizing an application in the Vitis unified software development environment. {Lecture}
  • C/C++ based Kernel Optimization
    Reviews different techniques such as loop unrolling, pipelining, and DATAFLOW. {Lecture}
  • Host Code Optimization
    Describes various optimization techniques, such as reducing the overhead of kernel enqueing and optimizing the data transfer between kernels and global memory. {Lecture}
  • Optimizing the Performance of the Design
    Illustrates various optimization techniques, such as optimizing the host code and data transfer between kernels and global memory, to improve kernel performance. {Lab}

Libraries
  • Vitis Accelerated Libraries
    Describes the Vitis accelerated libraries that are available for domain-specific and common libraries. These libraries are open-source, performance-optimized libraries that offer out-of-the-box acceleration. {Lecture}

Platform Creation
  • Creating a Vitis Embedded Acceleration Platform (Edge)
    Describes the Vitis embedded acceleration platform, which provides product developers an environment for creating embedded software and accelerated applications on heterogeneous platforms based on FPGAs, Zynq SoCs, and Alveo data center cards. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Basic knowledge of AMD FPGA architecture
  • Comfort with the C/C++ programming language (or equivalent training/experience)
  • Software development flow
  • Familiarity with makefiles

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Updated 8-18-2024
©2024 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

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