Vivado Boot Camp: Basic Training

This course is available as private training only.

Vivado Boot Camp: Basic Training, is targeted towards engineers with little to no AMD (Xilinx) knowledge or experience. It provides a fundamental understanding of AMD Silicon and Software.

Topics covered include device application areas and overviews of AMD silicon and Vivado tools.

See Course Outline

2-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$120012
In-Person Public Registration - $600/day$120012
Printed Course Book (A PDF book is included in the course fee)$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

This course is available as private training only.

Training Duration:

2 Days

We update our schedule regularly. Stay informed.

Who should attend:

Digital designers with basic knowledge of HDLs (VHDL or Verilog) who are new to AMD FPGAs.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Understand primary 7 series FPGA architecture resources
  • Make basic use of the Project Manager
  • Make basic use of the Schematic viewer and Hierarchical viewer
  • Synthesize and implement a simple HDL design
  • Review basic synthesis and implementation reports
  • Explore basic timing constraints
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

Course Outline

Day 1Day 2
  • UltraFast® Design Methodology Summary
  • FPGA Architecture Overview
  • Introduction to the Vivado Design Suite
  • LAB: Vivado Basic Tool Overview
  • Basic Timing Constraints and Reports
  • LAB: Vivado Synthesis, Implementation
  • Designing with FPGA Resources
  • Clocking Overview
  • LAB: Designing with FPGA Resources
  • Basic Timing Constraints (XDC)
  • FPGA Configuration
  • Appendix: SystemVerilog
  • Appendix: Design Methodology
  • Appendix: HDL Coding Techniques

Please note: The instructor may change the content order to provide a better learning experience.


  • Working HDL knowledge (VHDL or Verilog)
  • Digital design experience


Updated 12-08-2021