Vivado Boot Camp: Basic Training

Vivado Boot Camp: Basic Training, is targeted towards engineers with little to no Xilinx knowledge or experience. It provides a fundamental understanding of Xilinx Silicon and Software.

Topics covered include device application areas and overviews of Xilinx silicon and Vivado tools.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Understand primary 7 series FPGA architecture resources
  • Make basic use of the Project Manager
  • Make basic use of the Schematic viewer and Hierarchical viewer
  • Synthesize and implement a simple HDL design
  • Review basic synthesis and implementation reports
  • Explore basic timing constraints
  • Identify synchronous design techniques
  • Describe how an FPGA is configured

Course Outline

Day 1

  • UltraFast® Design Methodology Summary
  • FPGA Architecture Overview
  • Introduction to the Vivado Design Suite
  • LAB: Vivado Basic Tool Overview
  • Basic Timing Constraints and Reports
  • LAB: Vivado Synthesis, Implementation

Day 2

  • Designing with FPGA Resources
  • Clocking Overview
  • LAB: Designing with FPGA Resources
  • Basic Timing Constraints (XDC)
  • FPGA Configuration
  • Appendix: SystemVerilog
  • Appendix: Design Methodology
  • Appendix: HDL Coding Techniques

No Scheduled Sessions – Contact Us to ask about setting one up!

Education Investment Options

Standard Registration
Standard Registration
18 Training Credits
Advanced Registration
Advanced Registration
16 Training Credits
Basic Follow-on Coaching
Comprehensive Follow-on Coaching

  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.


Training Duration:

2 Days

Who should attend:

Digital designers with basic knowledge of HDLs (VHDL or Verilog) who are new to Xilinx FPGAs


  • Working HDL knowledge (VHDL or Verilog)
  • Digital design experience

Version: 2021-03-17_0932