Designing with the Zynq® Ultrascale+ RFSoC

This course provides an overview of the hard block capabilities for the Zynq® Ultrascale+ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.

The focus is on:

Describing the RFSoC family in general

Identifying applications for the Data Converter and SD-FEC blocks

Configuring, simulating, and implementing the blocks

Reviewing power estimation to help identify the power demands of the RFSoC device in various operating modes

Identifying proper layout and PCB considerationssince the Zynq® Ultrascale+ RFSoC is both a high-speed and an analog and digital device

Skills Gained

After completing this comprehensive training, you will know how to:

  • After completing this comprehensive training, you will know how to:
  • Describe in general the new Zynq® Ultrascale+ RFSoC family
  • Identify typical applications for the data converters
  • Describe the architecture and functionality of the ADC
  • Utilize the ADC via configuration, simulation, and implementation
  • Describe the architecture and functionality of the DAC
  • Utilize the DAC via configuration, simulation, and implementation
  • Identify the requirements and options for data converter PCB designs
  • Describe the architecture and functionality of the SD-FEC hard IP
  • Utilize the SD-FEC via configuration, simulation, and implementation

Course Outline

Introduction

  • Zynq® Ultrascale+ MPSoC Architectural Overview
  • RF Backgrounder
  • Zynq® Ultrascale+ RFSoC Hardware Overview
  • Zynq® Ultrascale+ RFSoC Data Converter Solutions Overview
  • Zynq® Ultrascale+ RFSoC SD-FEC Solutions Overview
  • Data Converter Driver Overview
  • Zynq® Ultrascale+ RFSoC ADC-DAC and SD-FEC Tool Support Overview

ADCs

  • RF-ADC Basics of ADCs
  • RF-ADC Architecture
  • RF-ADC Creating ADC System in IPI
  • RF-ADC Functionality
  • RF-ADC Interfaces
  • RF-ADC IP Configuration
  • RF-ADC Driver Overview

DACs

  • RF-DAC Basics of DACs
  • RF-DAC Architecture
  • RF-DAC Creating DAC System in IPI
  • RF-DAC Functionality
  • RF-DAC Interfaces
  • RF-DAC IP Configuration
  • RF-DAC Driver Overview

Data Converter IP

  • Data Converter Common Features
  • Data Converter Design Flow
  • Data Converter Example Design
  • Data Converter Simulation
  • Data Converter Implementation

Hardware Requirements

  • Zynq® Ultrascale+ RFSoC Power Requirements
  • Zynq® Ultrascale+ RFSoC Power Estimation
  • Zynq® Ultrascale+ RFSoC Power Design
  • Zynq® Ultrascale+ RFSoC Analog Signal Requirements
  • Zynq® Ultrascale+ RFSoC PCB Materials and Stackup
  • Zynq® Ultrascale+ RFSoC PCB Analog Trace Design

FEC

  • SD-FEC Basics of FEC
  • SD-FEC IP Architecture and Functionality
  • SD-FEC IP Configuration
  • SD-FEC IP Interfaces
  • SD-FEC Software Driver Overview
  • SD-FEC IP Usage

Scheduled Classes

Columbia, MD
6/27/2019 - 6/28/2019
Parsippany, NJ
7/11/2019 - 7/12/2019
Trevose, PA
7/11/2019 - 7/12/2019
Sterling, Virginia
7/11/2019 - 7/12/2019
Hauppauge, NY
7/18/2019 - 7/19/2019
Rochester, NY
7/25/2019 - 7/26/2019
Columbia, MD
10/31/2019 - 11/1/2019

Education Investment Options

Standard Registration
$1,600
Standard Registration
16 Training Credits
Advanced Registration
$1,400
Advanced Registration
14 Training Credits
Basic Follow-on Coaching
$500
Comprehensive Follow-on Coaching
$700
  • To qualify for the Advanced Registration Price, full payment must be received 21 days prior to the first day of class.
  • Basic follow-on coaching includes 2 hours (max 2 calls)
  • Comprehensive follow-on coaching includes 10 hours (max 5 calls)
  • Follow-on Coaching must be purchased at time of registration.
To Register For This Course Please Call 1-888-XILINX-1

Training Duration:

2 Days

Who should attend:

Hardware designers interested in understanding the architecture and capabilities of the Zynq® Ultrascale+ RFSoC data converter and SD-FEC hard blocks.

Prerequisites

Suggested: Understanding of the Zynq® Ultrascale+ MPSoC architecture

Basic familiarity with data converter terms and principles

Basic familiarity with forward error correction terms and principles

Software Tools

Vivado Design or System Edition 2018.1

Hardware

None

Last Updated: 2019-06-06_1626