Interfacing DDR with Programmable Logic on the Versal NoC – OnDemand Webinar

On-Demand Webinar

This introduction to the NoC will demonstrate how to quickly interface your PS and PL to DDR through the recently introduced ACAP NoC Architecture. The introduction will be followed by a live demo.

AMD Xilinx authorized training provider BLT (Bottom Line Technologies) presents this webinar.

To view the on-demand recording from our Interfacing DDR with Programmable Logic on the Versal NoC Webinar, please complete the form below. The link will be emailed to you.