BLT Webinar Series Schedule

BLT offers a free webinar series on topics ranging from Versal designs to managing FPGA projects and everything in between. Each webinar in the series will include a Q&A section at the end. We also offer no-cost 4-hour workshops, sponsored by AMD Xilinx.

Please fill out the form below to receive emails about the webinars and workshops series.

Complete List of Webinar Recordings and Upcoming No-Cost Events

Webinars: Up to an hour long.

Workshops: 4 or more hours long.

 

Missed registering for a webinar and the on-demand isn’t ready yet? Email [email protected].

COURSECLASS DATELOCATIONSTATUS
WEBINAR: Introduction to AXI: What Is AXI?November 1, 2023OnlineRecording Coming Soon
WEBINAR: Space Application RFSoCs / State MachinesNovember 15, 2023OnlineRecording Coming Soon
WEBINAR: Getting Started with the Kria SOMNovember 29, 2023OnlineRecording Coming Soon
WORKSHOP: Advanced Debugging (Sponsored by AMD Xilinx)December 13, 2023OnlineRegister
WEBINAR: Closing Timing Using Intelligent Design Flow (Spotlight: AMD New Tool Feature)January 31, 2024OnlineRegister
WORKSHOP: Implementing DSP Using Vitis Model Composer Workshop (Sponsored by AMD Xilinx)February 21, 2024OnlineRegister
WEBINAR: Debug Techniques for Vivado Block DesignsFebruary 28, 2024OnlineRegister
WORKSHOP: Mastering Vivado Timing Constraints: Strategies for FPGA Performance (Sponsored by AMD Xilinx)March 20, 2024OnlineRegister
WEBINAR: Demystifying Clock Domain Crossings (CDC) and Synchronization CircuitsMarch 27, 2024OnlineRegister
WORKSHOP: Adaptive SoCs 101: Quick Start Guide to Integration and Implementation (Sponsored by AMD Xilinx)April 23, 2024OnlineRegister
WEBINAR: Versal AI Engine Tool Flow Explained: Enhancing Your Development JourneyMay 1, 2024OnlineRegister
WORKSHOP: Versal Adaptive SOC: Network on Chip (Sponsored by AMD Xilinx)May 22, 2024OnlineRegister
WEBINAR: What is the AI Engine?May 29, 2024OnlineRegister
WORKSHOP: Adaptive Computing for Managers (Sponsored by AMD Xilinx)June 19, 2024OnlineRegister
WEBINAR: Maximizing Your Debug with System ILAsJune 26, 2024OnlineRegister
WORKSHOP: Unlocking AMD Embedded Software Essentials: Key Strategies & Techniques (Sponsored by AMD Xilinx)July 24, 2024OnlineRegister
WEBINAR: What is AMD AI Inference? Optimizing Model Deployment for Real-World ApplicationsJuly 31, 2024OnlineRegister
WORKSHOP: Advanced Debugging (Sponsored by AMD Xilinx)August 21, 2024OnlineRegister
WEBINAR: Increasing Design Performance Using Report QoRAugust 28, 2024OnlineRegister
WORKSHOP: Digital Logic 101 (Sponsored by AMD Xilinx)September 18, 2024OnlineRegister
WEBINAR: Advanced RFSoC Analysis with AMD: Leveraging the RF Analyzer Tool for In-Depth InsightsSeptember 25, 2024OnlineRegister
Webinar: Outsourcing Design Solutions for Defense PrimesOn-DemandRecordedWatch
Webinar: Understanding Verification for Digital DesignOn-DemandRecordedWatch
Webinar: Dark Mode in Vitis: The New IDEOn-DemandRecordedWatch
Webinar: HLS: What Is It and When Do You Use It?On-DemandRecordedWatch
Webinar: Engineering Roundtable: Verification of SoC DesignsOn-DemandRecordedWatch
Webinar: Getting Started with Kria SOMOn-DemandRecordedWatch
Webinar: BLT Engineering Roundtable - Design Productivity Tricks for Busy EngineersOn-DemandRecordedWatch
Webinar: Debugging Using Cross TriggeringOn-DemandRecordedWatch
Webinar: Accelerating AI with the Vitis Unified Software PlatformOn-DemandRecordedWatch
Webinar: Xilinx for ManagersOn-DemandRecordedWatch
Webinar: Interfacing DDR with Programmable Logic on the Versal NoCOn-DemandRecordedWatch

Past Webinars

Xilinx for Managers Webinar

Registration is closed. Available as an On-Demand video.

Interested in our Xilinx for Managers course, but not sure if the topics are right for you? Check out this free webinar to see what the course is all about.

Topics:
  • Xilinx devices – with a focus on Versal ACAPs
  • PSSST – Don’t be pissed! Instead use PSSST – a technique for project success.
  • Three Dirty Words

Interfacing DDR with Programmable Logic on the Versal NoC Webinar

Registration is closed. View the On-Demand video.

Join us as one of our top engineers talks about interfacing DDR with programmable logic on the AMD Xilinx Versal NoC.

This introduction to the NoC will demonstrate how to quickly interface your PS and PL to DDR through the recently introduced ACAP NoC Architecture. The introduction will be followed by a live demo and Q&A session.

Debugging Using Cross Triggering Webinar

Registration is closed. View the On-Demand video.

Often, hardware-only debuggers are sufficient for checking timing and ensuring proper behavior for peripherals. Simulation, such as bus-functional modeling or its equivalent, may also be used to verify that the peripheral is reacting properly to “bus” stimulus.

Software-only debuggers enable users to single-step or run to (conditional) breakpoints and check values of variables and regions in memory.

But what happens when hardware and software are connected? Custom peripherals may not always integrate seamlessly. Are the device drivers for the peripheral working properly? Are the user’s APIs? Is the hardware behaving the way the driver writer thought it should?

Cross-triggering or hardware-software debugging brings a new capability to the developer to quickly narrow down where the issues are and get them resolved.

This live demo will demonstrate cross-triggering debugging.

Accelerating AI with the Vitis Unified Software Platform Webinar

Registration is closed. View the On-Demand video.

In this webinar you’ll get an overview of the Vitis™ Unified Software Platform, including the Vitis platform acceleration model, the Vitis tool flow for on-premises, cloud and edge deployment, how the hardware acceleration boosts performance and the rules to remember for hardware acceleration.

You’ll also receive an overview of the frameworks supported by the Vitis AI, including what is Caffe and its features, TensorFlow and its features, Pytorch and its features, and the Vitis AI zoo repository.

Finally, we’ll go over the Vitis Software accelerated libraries for domain-specific libraries, common libraries, and how the Vitis accelerated libraries abstract the HW with L1, L2, and L3 level APIs.

The webinar will be followed by an open Q&A session.