BLT Webinar Series Schedule

BLT offers a free webinar series on topics ranging from Versal designs to managing FPGA projects and everything in between. Each webinar in the series will include a Q&A section at the end. We also offer no-cost 4-hour workshops, sponsored by AMD Xilinx.

Please fill out the form below to receive emails about the webinars and workshops series.

Complete List of Webinar Recordings and Upcoming No-Cost Events

Webinars: Up to an hour long.

Workshops: 4 or more hours long.

WEBINAR: Understanding Verification for Digital DesignSeptember 20, 2023OnlineRegister
WEBINAR: Outsourcing Design Solutions for Defense PrimesSeptember 27, 2023OnlineRegister
WORKSHOP: Adaptive Computing for ManagersOctober 17, 2023OnlineRegister
WEBINAR: Introduction to AXI: What Is AXI?November 1, 2023OnlineRegister
WEBINAR: Space Application RFSoCs / State MachinesNovember 15, 2023OnlineRegister
WEBINAR: Getting Started with the Kria SOMNovember 29, 2023OnlineRegister
WORKSHOP: Advanced Debugging (Sponsored by AMD Xilinx)December 13, 2023OnlineRegister
WEBINAR: Dark Mode in Vitis: The New IDEOn-DemandRecordedWatch
Webinar: HLS: What Is It and When Do You Use It?On-DemandRecordedWatch
Webinar: Engineering Roundtable: Verification of SoC DesignsOn-DemandRecordedWatch
Webinar: Getting Started with Kria SOMOn-DemandRecordedWatch
Webinar: BLT Engineering Roundtable - Design Productivity Tricks for Busy EngineersOn-DemandRecordedWatch
Webinar: Debugging Using Cross TriggeringOn-DemandRecordedWatch
Webinar: Accelerating AI with the Vitis Unified Software PlatformOn-DemandRecordedWatch
Webinar: Xilinx for ManagersOn-DemandRecordedWatch
Webinar: Interfacing DDR with Programmable Logic on the Versal NoCOn-DemandRecordedWatch

Past Webinars

Xilinx for Managers Webinar

Registration is closed. Available as an On-Demand video.

Interested in our Xilinx for Managers course, but not sure if the topics are right for you? Check out this free webinar to see what the course is all about.

  • Xilinx devices – with a focus on Versal ACAPs
  • PSSST – Don’t be pissed! Instead use PSSST – a technique for project success.
  • Three Dirty Words

Interfacing DDR with Programmable Logic on the Versal NoC Webinar

Registration is closed. View the On-Demand video.

Join us as one of our top engineers talks about interfacing DDR with programmable logic on the AMD Xilinx Versal NoC.

This introduction to the NoC will demonstrate how to quickly interface your PS and PL to DDR through the recently introduced ACAP NoC Architecture. The introduction will be followed by a live demo and Q&A session.

Debugging Using Cross Triggering Webinar

Registration is closed. View the On-Demand video.

Often, hardware-only debuggers are sufficient for checking timing and ensuring proper behavior for peripherals. Simulation, such as bus-functional modeling or its equivalent, may also be used to verify that the peripheral is reacting properly to “bus” stimulus.

Software-only debuggers enable users to single-step or run to (conditional) breakpoints and check values of variables and regions in memory.

But what happens when hardware and software are connected? Custom peripherals may not always integrate seamlessly. Are the device drivers for the peripheral working properly? Are the user’s APIs? Is the hardware behaving the way the driver writer thought it should?

Cross-triggering or hardware-software debugging brings a new capability to the developer to quickly narrow down where the issues are and get them resolved.

This live demo will demonstrate cross-triggering debugging.

Accelerating AI with the Vitis Unified Software Platform Webinar

Registration is closed. View the On-Demand video.

In this webinar you’ll get an overview of the Vitis™ Unified Software Platform, including the Vitis platform acceleration model, the Vitis tool flow for on-premises, cloud and edge deployment, how the hardware acceleration boosts performance and the rules to remember for hardware acceleration.

You’ll also receive an overview of the frameworks supported by the Vitis AI, including what is Caffe and its features, TensorFlow and its features, Pytorch and its features, and the Vitis AI zoo repository.

Finally, we’ll go over the Vitis Software accelerated libraries for domain-specific libraries, common libraries, and how the Vitis accelerated libraries abstract the HW with L1, L2, and L3 level APIs.

The webinar will be followed by an open Q&A session.