BLT offers a free webinar series on topics ranging from Versal® to managing FPGA projects and everything in between. Each webinar in the series will include a Q&A section at the end.
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May 20, 2022 @ 2 PM ET
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Join us as one of our top engineers talks about interfacing DDR with programmable logic on the AMD – Xilinx Versal NoC.
This introduction to the NoC will demonstrate how to quickly interface your PS and PL to DDR through the recently introduced ACAP NoC Architecture. The introduction will be followed by a live demo and Q&A session.
Registration is closed. View the On-Demand video.
Often, hardware-only debuggers are sufficient for checking timing and ensuring proper behavior for peripherals. Simulation, such as bus-functional modeling or its equivalent, may also be used to verify that the peripheral is reacting properly to “bus” stimulus.
Software-only debuggers enable users to single-step or run to (conditional) breakpoints and check values of variables and regions in memory.
But what happens when hardware and software are connected? Custom peripherals may not always integrate seamlessly. Are the device drivers for the peripheral working properly? Are the user’s APIs? Is the hardware behaving the way the driver writer thought it should?
Cross-triggering or hardware-software debugging brings a new capability to the developer to quickly narrow down where the issues are and get them resolved.
This live demo will demonstrate cross-triggering debugging.
Registration is closed. View the On-Demand video.
In this webinar you’ll get an overview of the Vitis™ Unified Software Platform, including the Vitis platform acceleration model, the Vitis tool flow for on-premises, cloud and edge deployment, how the hardware acceleration boosts performance and the rules to remember for hardware acceleration.
You’ll also receive an overview of the frameworks supported by the Vitis AI, including what is Caffe and its features, TensorFlow and its features, Pytorch and its features, and the Vitis AI zoo repository.
Finally, we’ll go over the Vitis Software accelerated libraries for domain-specific libraries, common libraries, and how the Vitis accelerated libraries abstract the HW with L1, L2, and L3 level APIs.
The webinar will be followed by an open Q&A session.
Registration is closed. Available as an On-Demand video.
Interested in our Xilinx for Managers course, but not sure if the topics are right for you? Check out this free webinar to see what the course is all about.
