BLT Webinar Series

BLT Webinars and Workshops Schedule

BLT offers a no-cost series of webinars and workshops on topics ranging from Versal designs to managing FPGA projects and everything in between. Each event in the series includes live instruction with Q&A with a BLT expert. Workshops are sponsored by AMD.

What’s the difference between a webinar and a workshop?

Webinars are 30 minutes to an hour long, and usually include one demo and a Q&A session with our topic expert. Webinars are available on-demand after the event.

Workshops are 4 hours long and include questions throughout and several demos. Workshops are not available on-demand.

Both event types include recordings sent to attendees after the event.

View Webinars

Sign up to hear about upcoming webinars:

Complete List of Upcoming No-Cost Events

COURSEEVENT DATELOCATIONSTATUS
Recordings of previous webinars are located in the table below this one.
WEBINAR: Enhancing System Reliability with the AMD Isolation Design Flow and Dynamic Function ExchangeOctober 30, 2024OnlineRecording Coming Soon
WORKSHOP: Digital Logic 101 (Sponsored by AMD)November 20, 2024OnlineRegister
WEBINAR: Build Flow for KRIA SOMNovember 26, 2024OnlineRegister
WORKSHOP: From Theory to Practice: Applying Timing Constraints (Sponsored by AMD)December 18, 2024 @ 10 AM ETOnlineRegister
WEBINAR: Understanding AXIDecember 19, 2024 @ 2 PM ETOnlineRegister
WEBINAR: Optimizing FPGA Designs with Vivado Reports and Design Rule ChecksJanuary 29, 2025 @ 2 PM ETOnlineRegister
WORKSHOP: Versal Adaptive SoCs Quick Start Workshop: A Guide to Integration and Implementation (Sponsored by AMD)January 22, 2025OnlineRegister
WORKSHOP: Vitis IDE Quick Start (Sponsored by AMD)February 19, 2025OnlineRegister

Complete List of Webinar Recordings

Missed registering for a webinar and the on-demand isn’t ready yet? Email [email protected].

COURSEEVENT DATELOCATIONSTATUS
Webinar: Advanced RFSoC Analysis with AMD: Leveraging the RF Analyzer Tool for In-Depth InsightsOn-DemandRecordedWatch
Webinar: Increasing Design Performance Using QoR ReportsOn-DemandRecordedWatch
Webinar: What Is AMD AI Inference? Optimizing Model Deployment for Real-World ApplicationsOn-DemandRecordedWatch
Webinar: Maximizing Your Debug with System ILAsOn-DemandRecordedWatch
Webinar: What Is the AI Engine?On-DemandRecordedWatch
Webinar: Versal AI Engine Tool Flow Explained: Enhancing Your Development JourneyOn-DemandRecordedWatch
Webinar: Demystifying Clock Domain Crossings (CDC) and Synchronization CircuitsOn-DemandRecordedWatch
Webinar: Debug Techniques for Vivado Block DesignsOn-DemandRecordedWatch
Webinar: Closing Timing Using Intelligent Design Runs (Spotlight on New AMD Tool Feature)On-DemandRecordedWatch
Webinar: Introduction to AXI: What Is AXI?On-DemandRecordedWatch
Webinar: Techniques for Space Applications - Including RFSoCs, Ruggedized Devices and Safe State MachinesOn-DemandRecordedWatch
Webinar: Getting Started with the Kria SOMOn-DemandRecordedWatch
Webinar: Outsourcing Design Solutions for Defense PrimesOn-DemandRecordedWatch
Webinar: Understanding Verification for Digital DesignOn-DemandRecordedWatch
Webinar: Dark Mode in Vitis: The New IDEOn-DemandRecordedWatch
Webinar: HLS: What Is It and When Do You Use It?On-DemandRecordedWatch
Webinar: Engineering Roundtable: Verification of SoC DesignsOn-DemandRecordedWatch
Webinar: BLT Engineering Roundtable - Design Productivity Tricks for Busy EngineersOn-DemandRecordedWatch
Webinar: Debugging Using Cross TriggeringOn-DemandRecordedWatch
Webinar: Accelerating AI with the Vitis Unified Software PlatformOn-DemandRecordedWatch
Webinar: Xilinx for ManagersOn-DemandRecordedWatch
Webinar: Interfacing DDR with Programmable Logic on the Versal NoCOn-DemandRecordedWatch

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