Advanced Debug Techniques for Hardware Engineers

COURSE CODE: BLT-DEBUG1

This 1-day course is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures, demonstrations and labs, along with general debugging concepts, tools and techniques.

Additionally, this course will cover common gotchas and roadblocks engineers commonly face when both implementing FPGA designs and bringing up PCBs for the first time. The hands-on labs provide students with experience designing, expanding and modifying an embedded system, including techniques for triggering on boot and hardware-software co-debugging.

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$600	6
In-Person Registration - $600/day	$600	6
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

1 Day

To see our Advanced Debugging Workshop, go here.

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Who should attend:

Hardware engineers, system architects, and anyone who wants to learn how to debug challenging issues encountered while developing with FPGAs, SoCs, Adaptive SoCs, and PCBs.

Skills Gained

After completing this comprehensive training, you will know how to:

Identify synchronous design techniques
Use the Vivado logic analyzer and debug flows to debug a design
Debug a design with multiple clock domains with the help of multiple debug cores using the Vivado logic analyzer
Debug a design at the device startup phase to debug issues related to startup events, such as MMCM lock and design coming out of reset

Course Outline

Day 1
Vivado Debug Methodology Introduction to Vivado Logic Analyzer Debug Cores – Overview Netlist Insertion Flow Lab: Inserting a Debug Core Using the Netlist Insertion Flow HDL Instantiation Flow Lab: Adding a Debug Core Using the HDL Instantiation Flow Introduction to Triggering Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Lab: Triggering Using the Trigger State Machine Capturing Data in Multiple Clock Domains Lab: Sampling and Capturing Data in Multiple Clock Domains Trigger and Debug at Device Startup Debugging Using TCL Commands Lab: Debugging a Design Using Tcl Commands Transceiver Test and Debugging Lab: IBERT Lab on the ZCU104 Board

Day 1

Vivado Debug Methodology
Introduction to Vivado Logic Analyzer
Debug Cores – Overview Netlist Insertion Flow
Lab: Inserting a Debug Core Using the Netlist Insertion Flow
HDL Instantiation Flow
Lab: Adding a Debug Core Using the HDL Instantiation Flow
Introduction to Triggering
Trigger Using the Trigger State Machine in the Vivado Logic Analyzer
Lab: Triggering Using the Trigger State Machine
Capturing Data in Multiple Clock Domains
Lab: Sampling and Capturing Data in Multiple Clock Domains
Trigger and Debug at Device Startup
Debugging Using TCL Commands
Lab: Debugging a Design Using Tcl Commands
Transceiver Test and Debugging
Lab: IBERT Lab on the ZCU104 Board

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Working HDL knowledge (VHDL or Verilog)
Digital or system design experience

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Updated 8-18-2024

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