Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite

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Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite (formerly Partial Reconfiguration)

COURSE CODE: FPGA-DFX

Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.

The emphasis of this course is on:

  • Identifying best design practices and understanding the subtleties of the DFX design flow
  • Using the DFX Controller and DFX Decoupler IP in the DFX process
  • Implementing DFX in an embedded system environment
  • Applying appropriate debugging techniques on DFX designs
  • Employing best practice coding styles for a DFX system

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$1001
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More

Scheduled Classes

Live Online Training (9am-5pm ET)
December 3-5, 2024 | Register Today
View our Full Calendar for class date status.
(Confirmed, Closed, Full)

Training Duration:

2 Days

REGISTER

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

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Who should attend:

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and digital design and who want to implement Dynamic Function eXchange techniques.

Software Tools

  • Vivado Design Suite
  • Vitis Unified Software Platform

Hardware

  • Architecture: UltraScale FPGAs and Versal adaptive SoCs
  • Demo board:
    • Zynq UltraScale+ MPSoC ZCU104 board
    • Versal adaptive SoC VCK190 board

Skills Gained

fAfter completing this comprehensive training, you will have the necessary skills to:

  • Describe what Dynamic Function eXchange is
  • Define DFX regions and reconfigurable modules with the Vivado Design Suite
  • Generate the appropriate full and partial bitstreams for a DFX design
  • Implement a nested DFX design
  • Enable the Abstract Shell feature in project mode
  • Use the ICAP and PCAP components to deliver partially reconfigurable systems
  • Implement a DFX system using the DFX Controller IP
  • Use the block design container feature of the Vivado IP integrator to create a DFX design
  • Identify how Dynamic Function eXchange affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
  • Implement a Dynamic Function eXchange system using the following techniques:
    • Direct JTAG connection, floorplanning, and timing constraints and analysis
  • Debug a DFX design using the Vivado Design Suite
  • Implement a DFX system in an embedded environment using the Vitis IDE

Course Outline

Day 1Day 2
Basics of DFX
  • Introduction to Dynamic Function eXchange (DFX)
    Explains what Dynamic Function eXchange is and defines the terminologies used in DFX. Also provides an overview of the configuration and reconfiguration processes. {Lecture, Demo}
    DFX Tool Flow
    • DFX Flow Using the Vivado Design Suite GUI
      Illustrates the steps for creating a DFX project in the Vivado Design Suite and describes various supported and unsupported features. {Lecture, Lab}
    • DFX Flow Using Vivado Design Suite Tcl Commands
      Reviews the flow using non-project-based commands, including using implementation constraints and specific characteristics {Lecture, Lab}
    • Nested DFX
      Describes using nested DFX, the process by which a Reconfigurable Partition (RP) can be segmented into smaller regions, each of which is partially reconfigurable. {Lecture, Lab}
    • Abstract Shell for Dynamic Function eXchange
      Describes how compilation time can be reduced by using an Abstract shell (UltraScale+ devices only). {Lecture}
    DFX Design Considerations for AMD Devices
    • DFX Design Considerations for All AMD Devices
      Covers the requirements, characteristics, and limitations associated with DFX designs that can simplify the debug process and reduce the risk of design malfunctions. {Lecture}
    • DFX Design Considerations for 7 Series, Zynq SoC, UltraScale, and UltraScale+ Devices
      Discusses DFX design consideration methodologies for various Xilinx device families. {Lecture}
    • DFX Design Considerations for Versal Devices
      Describes the DFX design requirements that are specific to Versal devices. {Lecture}
    DFX Design-Specific IP Blocks
    • DFX Intellectual Property (IP)
      Reviews the various IPs that are specifically for use with DFX designs. {Lecture, Lab, Demo}
    • DFX Block Design Containers in IP Integrator
      Describes the block design container feature and how BDCs enable DFX. {Lecture, Lab}
    		DFX Configuration
    • Configuring Devices Using DFX
      Reviews the basics of configuration and various configuration modes. {Lecture}
    • Configuration Parameters
      Covers various configuration parameters, including factors that affect configuration time and configuration debugging. {Lecture}
    • DFX Bitstreams Describes the different types of bitstreams for DFX compilation, including full, partial, blanking, and clearing. {Lecture}
    • DFX Bitstream Integrity Describes partial bit file integrity and implementing DFX through the ICAP for FPGA devices. {Lecture}

    DFX Design Analysis and Debugging
    • Floorplanning a DFX Design
      Demonstrates how to create Pblocks for various devices and how to create a floorplan for a reconfigurable region. {Lecture, Lab}
    • DFX Timing Analysis and Constraints
      Illustrates how and when to apply different constraint files, the process of performing a DFX timing-level simulation, and the process of performing static timing analysis on a DFX design. {Lecture, Lab}
    • DFX Debugging
      Illustrates DFX debugging techniques using Vivado Design Suite debug cores. {Lecture, Lab}

    DFX Designs in Embedded Systems
    • DFX in Embedded Systems
      Describes the embedded design flow in the Vivado Design Suite, the advantages of using a processor with DFX, and how to connect a processor to the PCAP to control DFX using the Vitis IDE. {Lecture, Lab}
    • DFX Designs Using the PCIe Core
      Reviews the advantages of using a PCIe core in a DFX design. {Lecture}

    Please note: The instructor may change the content order to provide a better learning experience.

    Prerequisites:

    • Knowledge of VHDL or Verilog
    • Experience with the Vivado Design Suite
    • Moderate familiarity with digital design techniques
    • Experience with Tcl
    • Moderate familiarity with the project mode and non-project batch mode flow in the Vivado Design Suite

    RELATED COURSES:

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    Updated 12-08-2021
    Updated 8-18-2024
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