Designing with the Versal Adaptive SoC: Power and Board Design

COURSE CODE: ACAP-POWER-BD

This course provides a system-level understanding of power and thermal issues related to designing with the AMD Versal adaptive SoC. PCB design considerations for the Versal devices are also covered.

The emphasis of this course is on:

Estimating power using power analysis
Managing thermal design
Understanding Versal device packaging
Implementing proper pin-to-board connection
Using the Schematic Review Checklist to validate a PCB design

Click here for more information about the AMD Versal Adaptive SoC.

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1200	12
In-Person Public Registration - $600/day	$1200	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

2 Days

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Be the first to know. Sign up for our newsletter.

Who should attend:

Hardware designers and system architects wanting to develop an effective power distribution network for the Versal device.

Software Tools

Vivado Design Suite
Power Design Manager tool

Hardware

Architecture: AMD Versal Adaptive SoC

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Design an efficient power distribution network for AMD Versal adaptive SoC designs
Leverage the Power Design Manager tool for power estimation
Dynamically manage power consumption
Solve thermal challenges
Apply PCB design guidelines for board interfaces with Versal devices

Course Outline

Day 1	Day 2
AMD Versal Adaptive SoC Architecture Overview for Existing Users Introduces to students who already have familiarity with AMD architectures the new and updated features found in the Versal devices. {Lecture} Power Solutions Overview Introduces key power concepts and explores some of capabilities of the Versal devices and introduces the power distribution network flow. {Lecture} Packaging and Power Integrity Describes key elements when modeling a PDN and dives deeper into packaging considerations. {Lecture} Thermal Solutions Overview Introduces key thermal concepts and explores some of the capabilities of the Versal devices. {Lecture} Power Management Discusses power domains and how they can be controlled along with basic techniques used to lower overall power consumption. {Lecture, Demo} Power Design Manager Discusses using the new Power Design Manager tool, including import and export functions. {Lecture, Lab} Power Reduction Techniques Describes various options to reduce power during the design process. {Lecture} Power Supply Backgrounder Reviews linear and switching power supplies and common terms used to specify power supply characteristics. {Lecture}	Board System Design Overview Introduces PCB design topics. {Lecture} Designing the Power Supply Consolidates the thermal management concepts of the course for achieving a successful design. {Lecture} Designing PL Interfaces Focuses on bank structure and physical organization of the PL package pins. {Lecture} Designing PS Interfaces Covers the unique features of the dedicated PS I/O interface along with pin-planning techniques. {Lecture} Designing Memory Interfaces Discusses high-speed connections, routing, and design guidelines for DDR memories. {Lecture} Designing Transceiver Interfaces Describes the serial transceiver organization and proper trace requirements. {Lecture} PCB Simulation – Introduction to Signal Integrity Discusses reflection and crosstalk effects and provides options to minimize both effects. Introduces memory and serial transceiver IBIS simulation. {Lecture}

Day 1

Day 2

AMD Versal Adaptive SoC Architecture
Overview for Existing Users Introduces to students who already have familiarity with AMD architectures the new and updated features found in the Versal devices. {Lecture}

Power Solutions Overview
Introduces key power concepts and explores some of capabilities of the Versal devices and introduces the power distribution network flow. {Lecture}

Packaging and Power Integrity
Describes key elements when modeling a PDN and dives deeper into packaging considerations. {Lecture}

Thermal Solutions Overview
Introduces key thermal concepts and explores some of the capabilities of the Versal devices. {Lecture}

Power Management
Discusses power domains and how they can be controlled along with basic techniques used to lower overall power consumption. {Lecture, Demo}

Power Design Manager
Discusses using the new Power Design Manager tool, including import and export functions. {Lecture, Lab}

Power Reduction Techniques
Describes various options to reduce power during the design process. {Lecture}

Power Supply Backgrounder
Reviews linear and switching power supplies and common terms used to specify power supply characteristics. {Lecture}

Board System Design Overview
Introduces PCB design topics. {Lecture}

Designing the Power Supply
Consolidates the thermal management concepts of the course for achieving a successful design. {Lecture}

Designing PL Interfaces
Focuses on bank structure and physical organization of the PL package pins. {Lecture}

Designing PS Interfaces
Covers the unique features of the dedicated PS I/O interface along with pin-planning techniques. {Lecture}

Designing Memory Interfaces
Discusses high-speed connections, routing, and design guidelines for DDR memories. {Lecture}

Designing Transceiver Interfaces
Describes the serial transceiver organization and proper trace requirements. {Lecture}

PCB Simulation – Introduction to Signal Integrity
Discusses reflection and crosstalk effects and provides options to minimize both effects. Introduces memory and serial transceiver IBIS simulation. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Designing with the Versal Adaptive SoC: Architecture course
Familiarity with the Vivado Design Suite

RELATED COURSES:

Updated 12-18-2023

©2023 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.