Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users
Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users
This course is available as private training only.
COURSE CODE: FPGA-VAXDC4ISE
This course will update experienced ISE software users on how to utilize the AMD Xilinx Vivado Design Suite.
The emphasis is on:
- Reviewing the underlying database and static timing analysis (STA) mechanisms
- Utilizing Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports
- Applying appropriate timing constraints for SDR, DDR, sourcesynchronous, and system-synchronous interfaces
- Creating path-specific, false path, and min/max timing constraints as well as learning about timing constraint priority in the Vivado timing engine
- Utilizing a project-based scripting flow
- Employing FPGA design best practices and the UltraFast Design Methodology to improve design speed and reliability
Scheduled Classes
No Scheduled Sessions - Contact Us to ask about setting one up!
Training Duration:
2 Days
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Who should attend:
Existing Xilinx ISE Design Suite FPGA designers.
Software Tools
- Vivado Design or System Edition 2018.1
Hardware
- Architecture: UltraScale and 7 series FPGAs*
- Demo board: None*
* This course focuses on the UltraScale and 7 series architectures.
Skills Gained
After completing this comprehensive training, you will know how to:
- Create appropriate clock and input, output delay constraints and describe timing reports that involve input and output paths
- Analyze different timing reports
- Define a properly constrained design
- Describe setup and hold checks and describe the components of a timing report
- Identify key areas to optimize your design to meet your design goals and performance objectives
- Describe all of the options available with the report_timing and report_timing_summary commands
- Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
- Describe the timing constraints required to constrain systemsynchronous and source-synchronous interfaces
Course Outline
Please note: The instructor may change the content order to provide a better learning experience.
Prerequisites:
- Completion of the Vivado Design Suite for ISE Project Navigator Users course is strongly recommended.
- Working HDL knowledge (VHDL or Verilog)
- Digital Design Experience