Designing with the Versal Adaptive SoC: Architecture

Course Code: ACAP-VARCH

Learn about the AMD Versal adaptive SoC architecture building blocks, such as Adaptable Engines, high-speed I/O, clocking, Scalar Engines, Intelligent Engines, and the programmable network on chip (NoC). Also learn how to use leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application.

The emphasis of this course is on:

Reviewing the architecture of the Versal adaptive SoC
Describing the different engines available in the Versal architecture and what resources they contain
Describing the architectures of the network on chip (NoC) and AI Engine
Outlining the memory solutions and programming interfaces available in the Versal adaptive SoC
Identifying the PCI Express® and serial transceiver solutions available in the Versal adaptive SoC

See Course Outline

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

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Who should attend:

Software and hardware developers, system architects, DSP users, and anyone who wants to learn about the architecture of the Versal adaptive SoC.

SOFTWARE:

Vivado Design Suite
Vitis Unified Software Platform

HARDWARE:

Architecture: Versal adaptive SoC
Demo board: Versal VCK190 Evaluation Platform

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe the AMD Versal adaptive SoC architecture
Identify the different engines available in the Versal devices and what resources they contain
Utilize the hardened blocks available in the Versal architecture
Describe the NoC and AI Engine architectures
Outline the memory solutions and programming interfaces available in the Versal adaptive SoC
Identify the PCI Express and serial transceiver solutions available in the Versal adaptive SoC
Follow the high-level system migration recommendations provided in this course

Course Outline

Day 1	Day 2	Day 3
Introduction Describes the need for Versal devices and offers an overview of the Versal portfolio. {Lecture} Architecture Overview Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture. {Lecture} Design Tool Flow Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab} Adaptable Engines (PL) Describes the logic resources available in the Adaptable Engine. {Lecture} SelectIO Resources Describes the I/O bank, SelectIO™ interface, and I/O delay features. {Lecture} Clocking Architecture Discusses the clocking architecture, clock buffers, clock routing, clock management functions, and clock de-skew. {Lecture, Lab}	Processing System Reviews the Arm® Cortex®-A72 processor APU and Cortex-R5 processor RPU that form the Scalar Engine. The platform management controller (PMC), processing system manager (PSM), I/O peripherals, and PS-PL interfaces are also covered. {Lecture} PMC and Boot and Configuration Describes the platform management controller, platform loader and manager (PLM) software and boot and configuration. {Lecture, Lab} System Interrupts Discusses the different system interrupts and interrupt controllers. {Lecture} Timers, Counters, and RTC Provides an overview of timers and counters, including the system counter, triple timer counter (TTC), watchdog timer, and real-time clock (RTC). {Lecture} DSP Engine Describes the DSP58 slice and compares the DSP58 slice with the DSP48 slice. DSP58 modes and applications are also covered in detail. {Lecture, Lab} AI Engine Discusses the AI Engine array architecture, terminology, and AIE interfaces. {Lecture, Lab}	NoC Introduction and Concepts Covers the reasons to use the network on chip, its basic elements, and common terminology. {Lecture, Lab} Memory Solutions Describes the available memory resources, such as block RAM, UltraRAM, LUTRAM, embedded memory, OCM, and DDR. The integrated memory controllers are also covered. {Lecture} Programming Interfaces Reviews the various programming interfaces in the Versal device. {Lecture} PCI Express & CCIX Provides an overview of the CCIX PCIe module and describes the PL and CPM PCIe blocks. {Lecture, Lab} Serial Transceivers Describes the transceivers in the Versal device. {Lecture} System Migration Compares the various functional blocks of the Versal devices to previous-generation devices. Describes the migration of designs from the UltraScale and UltraScale+ architectures to the Versal architecture. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of AMD FPGAs and adaptive SoCs
Basic knowledge of the Vivado and Viti tools

RELATED COURSES:

Updated 8-18-2024

©2024 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

Designing with the Versal Adaptive SoC: Architecture