Verification with SystemVerilog

COURSE CODE: LANG-SVVER

BLT offers a combined course for this material: Designing and Verification with SystemVerilog

This course provides an introduction to SystemVerilog constructs for verification.

This emphasis is on:

Writing testbenches to verify a design under test (DUT) utilizing the constructs available in SystemVerilog
Reviewing object-oriented modeling, data types, reusable tasks and functions, randomization, code coverage, assertions, the Direct Programming Interface (DPI), and interprocess communication

In this two-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1200	12
In-Person Public Registration - $600/day	$1200	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

2 Days

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

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Who should attend:

Hardware and verification engineers.

Software Tools

Vivado Design Suite

Hardware

Architecture: N/A*
Demo board: None*

* This course does not focus on any particular architecture

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe the advantages and enhancements to SystemVerilog to support verification
Define the new data types available in SystemVerilog
Analyze and use the improvements to tasks and functions
Discuss and use the various new verification building blocks available in SystemVerilog
Describe object-oriented programming and create a class-based verification environment
Explain the various methods for creating random data
Create and utilize random data for generating stimulus to a DUT
Identify how SystemVerilog enhances functional coverage for simulation verification
Utilize assertions to quickly identify correct behavior in simulation
Identify how the direct programming interface can be used with C/C++ in a verification environment
Describe the interprocess communication and threads

Course Outline

Day 1	Day 2
Introduction to SystemVerilog for Verification Provides an introduction to the SystemVerilog language. {Lecture} Data Types Explains SystemVerilog data types and arrays, such as fixed-size arrays, dynamic arrays, and associative arrays. {Lecture} Tasks and Functions Reviews SystemVerilog tasks and functions {Lecture, Lab} SystemVerilog Verification Building Blocks Describes SystemVerilog verification building blocks, such as program, interface, clocking, and packages. {Lecture, Lab} Object-Oriented Modeling Introduces object-oriented modeling, such as encapsulation, inheritance, and polymorphism. {Lecture, Lab}	Randomization Illustrates randomization methods, such as randcase, random sequence, and class-based randomization. {Lecture, Lab} Coverage Describes functional coverage and usage of covergroup, coverpoint, and bins. {Lecture, Lab} Assertions Reviews the different types of assertions. {Lecture, Lab} Direct Programming Interface Introduces the Direct Programming Interface (DPI) for interacting with C languages. {Lecture, Demo} Interprocess Communication Describes the interprocess communication between the different processes used to model a complex system. {Lecture}

Day 1

Day 2

Introduction to SystemVerilog for Verification
Provides an introduction to the SystemVerilog language. {Lecture}

Data Types
Explains SystemVerilog data types and arrays, such as fixed-size arrays, dynamic arrays, and associative arrays. {Lecture}

Tasks and Functions
Reviews SystemVerilog tasks and functions {Lecture, Lab}

SystemVerilog Verification Building Blocks
Describes SystemVerilog verification building blocks, such as program, interface, clocking, and packages. {Lecture, Lab}

Object-Oriented Modeling
Introduces object-oriented modeling, such as encapsulation, inheritance, and polymorphism. {Lecture, Lab}

Randomization
Illustrates randomization methods, such as randcase, random sequence, and class-based randomization. {Lecture, Lab}

Coverage
Describes functional coverage and usage of covergroup, coverpoint, and bins. {Lecture, Lab}

Assertions
Reviews the different types of assertions. {Lecture, Lab}

Direct Programming Interface
Introduces the Direct Programming Interface (DPI) for interacting with C languages. {Lecture, Demo}

Interprocess Communication
Describes the interprocess communication between the different processes used to model a complex system. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Designing with Verilog course
RTL coding using Verilog HDL
Basic digital design concepts
Understanding of flip-flops and logic gates
Basic understanding of synchronous design

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Updated 8-18-2024

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