Achieving Timing Closure in FPGA Designs Workshop

Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure.

Gain hands-on experience with timing closure techniques and learn strategies to improve design performance and meet timing requirements efficiently.

Gain experience with:

Understanding basic Static Timing Analysis (STA)
Reading timing report
Applying techniques to reduce delay and to improve clock skew and clock uncertainty
Resolving timing violations
Using the Timing Constraints Wizard

This course focuses on the UltraScale, UltraScale+ and Versal architectures.

COST:

AMD is sponsoring this workshop, with no cost to students. Limited seats available.

SCHEDULED EVENTS

Live Online Training (10am-3pm ET)

October 22, 2025

Training Duration:

1 Day (6 hours)

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Who should attend:

Digital designers, FPGA designers, and developers who need to learn timing closure in FPGA designs.

Skills Gained

After completing this comprehensive training, you will know how to:

Perform clocking and static timing analysis (STA)
Apply clock and I/O timing constraints and perform timing analysis
Analyze a timing report to identify how to center the clock in the data eye
Apply appropriate techniques to reduce logic and net delay and to improve clock skew and clock uncertainty
Apply baseline constraints to determine if internal timing paths meet design timing objectives

Course Outline

Day 1
Static Timing Analysis (STA) Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA). Setup and Hold Violation Analysis Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis. Generated Clocks Demonstrates using the report clock networks report to determine if there are any generated clocks in a design. UltraFast Design Methodology: Timing Closure Introduces the UltraFast methodology guidelines on timing closure. Timing Constraints Wizard Reviews how use the Timing Constraints Wizard to apply missing timing constraints in a design. DEMO: Baselining DEMO: Pipelining DEMO: Improving Clock Uncertainty

Day 1

Static Timing Analysis (STA)
Describes the clock and its attributes, basics of clock gating, and static timing analysis (STA).

Setup and Hold Violation Analysis
Covers what setup and hold slack are and describes how to perform input/output setup and hold analysis.

Generated Clocks
Demonstrates using the report clock networks report to determine if there are any generated clocks in a design.

UltraFast Design Methodology: Timing Closure
Introduces the UltraFast methodology guidelines on timing closure.

Timing Constraints Wizard
Reviews how use the Timing Constraints Wizard to apply missing timing constraints in a design.

DEMO: Baselining

DEMO: Pipelining

DEMO: Improving Clock Uncertainty

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Basic knowledge of the VHDL or Verilog language
Digital design knowledge

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Updated 03-12-2025

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