Migrating from UltraScale+ Devices to Versal Adaptive SoCs Workshop
Migrating from UltraScale+ Devices to Versal Adaptive SoCs Workshop
This course illustrates the different approaches for efficiently migrating existing designs to the AMD Versal™ adaptive SoC from AMD UltraScale+™ devices. The course also covers system design planning and partitioning methodologies as well as design migration considerations for different system design types.
The emphasis of this course is on:
- Identifying and comparing various functional blocks in the Versal adaptive SoC to those in previous-generation UltraScale+ devices
- Describing the development platforms for all developers
- Reviewing the approaches for migrating existing designs to the Versal adaptive SoC
- Specifying the recommended methodology for planning a system design migration based on the system design type
- Discussing AI Engine system partitioning planning
- Identifying design migration considerations for PL-only designs and Zynq™ UltraScale+ MPSoC designs
- Migrating Zynq UltraScale+ MPSoC-based system-level designs to the Versal adaptive SoC
- Detailing Versal device hardware debug features
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
SCHEDULED EVENTS
Live Online Training (10am-4pm ET)
Training Duration:
10am – 4pm
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Who should attend:
Software and hardware developers, system architects, and anyone who needs to migrate their designs to Versal devices.
Skills Gained
After completing this comprehensive training, you will know how to:
- Identify the different functional blocks in the AMD Versal adaptive SoC
- Describe the different tool flows for the Versal adaptive SoC
- Utilize high-level system migration steps for efficient migration to the Versal adaptive SoC
- Follow the system design planning methodology
- Apply design migration guidelines for PL-only and PS+PL designs
- Describe the AI Engine architecture and programming model as well as follow the AIE system partitioning methodology
- Migrate AMD Zynq UltraScale+ MPSoC system-level designs to the Versal adaptive SoC
- Describe the different debugging options available for the Versal adaptive SoC
Prerequisites:
- Familiarity with designing UltraScale+ FPGAs and adaptive SoCs
- Familiarity with the AMD Vivado and Vitis tools