Migrating from UltraScale+ Devices to Versal Adaptive SoCs

COURSE CODE: VER MGRT

This course illustrates the different approaches for efficiently migrating existing designs to the AMD Versal™ adaptive SoC from AMD UltraScale+ devices. The course also covers system design planning and partitioning methodologies as well as design migration considerations for different system design types.

The emphasis of this course is on:

Identifying and comparing various functional blocks in the Versal adaptive SoC to those in previous-generation UltraScale+ devices
Reviewing the approaches for migrating existing designs to the Versal adaptive SoC
Describing the development platforms for all developers
Enabling top-level RTL flows for Versal devices
Identifying design migration considerations for PL-only designs and Zynq™ UltraScale+ MPSoC designs
Specifying the recommended methodology for planning a system design migration based on the system design type
Discussing AI Engine system partitioning planning
Migrating Zynq UltraScale+ MPSoC-based system-level designs to the Versal adaptive SoC
Detailing Versal device hardware debug features

See Course Outline

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$600	6
In-Person Registration - $600/day	$600	6
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee)	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

1 Day

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

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Who should attend:

Software and hardware developers, system architects, and anyone who needs to migrate their designs to Versal
devices.

Software Tools

Vivado Design Suite
Vitis Unified IDE

Hardware

Architecture: Versal adaptive SoC

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Identify the different functional blocks in the AMD Versal adaptive SoC
Utilize high-level system migration steps for efficient migration to the Versal adaptive SoC
Describe the different tool flows for the Versal adaptive SoC
Implement a basic Versal NoC design
Utilize top-level RTL flows such as the modular NoC flow and GT subsystem flow for Versal devices
Apply design migration guidelines for PL-only and PS+PL designs
Follow the system design planning methodology
Describe the AI Engine architecture and programming model as well as follow the AIE system partitioning methodology
Migrate AMD Zynq UltraScale+ MPSoC system-level designs to the Versal adaptive SoC
Describe the different debugging options available for the Versal adaptive SoC

Course Outline

Day 1
Architecture Overview for Existing Users Introduces to students who already have familiarity with AMD SoC architectures the new and updated features found in the Versal devices. Also provides an overview of the Versal portfolio. {Lecture} System Design Migration Approach Describes important system design migration considerations and the high-level system steps for efficient migration to the Versal adaptive SoC. Also compares various functional blocks in the Versal adaptive SoC to those in previous-generation devices. {Lecture} Design Tool Flow Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture} NoC Introduction and Concepts Covers the reasons to use the network on chip, its basic elements, design entry flows, and common terminology. {Lecture, Lab} Enabling Top-level RTL Flows Discusses two RTL-centric flows: One for accessing the NoC from RTL, known as the modular NoC flow, and another for the gigabit transceivers with the GT Wizard Subsystem flow. {Lecture, Labs} Programmable Logic Design Migration Considerations Describes Versal adaptive SoC architectural enhancements as well as key programmable logic design migration considerations and best practices. Also covers the advantages of the Advanced Flow for Versal devices. {Lecture, Labs} Processing System Comparison Describes Versal adaptive SoC processing system architectural differences. It covers the differences in the boot sequence between Versal and Zynq UltraScale+ devices. Also introduces the segmented configuration feature for Versal devices. {Lecture} System Design Planning Methodology Describes system design planning, power, and thermal guidelines. Also reviews system debug, verification, and validation planning. {Lecture}

Day 1

Architecture Overview for Existing Users
Introduces to students who already have familiarity with AMD SoC architectures the new and updated features found in the Versal devices. Also provides an overview of the Versal portfolio. {Lecture}

System Design Migration Approach
Describes important system design migration considerations and the high-level system steps for efficient migration to the Versal adaptive SoC. Also compares various functional blocks in the Versal adaptive SoC to those in previous-generation devices. {Lecture}

Design Tool Flow
Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture}

NoC Introduction and Concepts
Covers the reasons to use the network on chip, its basic elements, design entry flows, and common terminology. {Lecture, Lab}

Enabling Top-level RTL Flows
Discusses two RTL-centric flows: One for accessing the NoC from RTL, known as the modular NoC flow, and another for the gigabit transceivers with the GT Wizard Subsystem flow. {Lecture, Labs}

Programmable Logic Design Migration Considerations
Describes Versal adaptive SoC architectural enhancements as well as key programmable logic design migration considerations and best practices. Also covers the advantages of the Advanced
Flow for Versal devices. {Lecture, Labs}

Processing System Comparison
Describes Versal adaptive SoC processing system architectural differences. It covers the differences in the boot sequence between Versal and Zynq UltraScale+ devices. Also introduces
the segmented configuration feature for Versal devices. {Lecture}

System Design Planning Methodology
Describes system design planning, power, and thermal guidelines. Also reviews system debug, verification, and validation planning. {Lecture}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Familiarity with designing UltraScale+ FPGAs and adaptive SoCs
Familiarity with the AMD Vivado and Vitis tools

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Updated 08-29-2025

©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.