Get to Know AMD Spartan UltraScale+ Devices for Real-World Designs Workshop
Get to Know AMD Spartan UltraScale+ Devices for Real-World Designs Workshop
The focus of this workshop is on learning the key features and architecture of the AMD Spartan UltraScale+ FPGA, including its advanced I/O, high-speed transceivers, substantial built-in and external memory, PCIe Gen4 connectivity, and modern security. Recognize how these features provide a versatile, cost-optimized, and power-efficient platform for diverse applications.
The emphasis of this course is on:
- Describing the key features and fundamental blocks of the Spartan UltraScale+ FPGA architecture
- Describing Spartan UltraScale+ clocking, including buffer types, clock management tiles, and routing for enhanced timing
- Describing the various on-chip memory resources available in the Spartan UltraScale+ architecture
- Utilizing the advanced I/O capabilities for various connectivity needs
- Identifying the high-speed transceivers for use in applications such as PCIe Gen4
COST:
AMD is sponsoring this workshop, with no cost to students. Limited seats available.
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Who should attend:
Anyone who would like to build a design for the Spartan UltraScale+ device.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Describe the key features and fundamental blocks of the AMD Spartan UltraScale+ FPGA architecture
- Describe Spartan UltraScale+ clocking, including buffer types, clock management tiles, and routing for enhanced timing
- Describe the various on-chip memory resources available in the Spartan UltraScale+ architecture
- Utilize the advanced I/O capabilities for various connectivity needs
- Identify the high-speed transceivers for use in applications such as PCIe Gen4
Course Outline
| Day 1 |
|---|
| Introduction to the AMD UltraScale+ Families Describes how UltraScale+ architectural benefits and features deliver enhanced performance, efficiency, and flexibility across diverse product families. {Lecture} Introduction to the AMD Spartan UltraScale+ Architecture Discusses the key features and fundamental blocks of the Spartan UltraScale+ architecture. {Lecture} Programmable Logic Explores the Spartan UltraScale+ programmable logic architecture, including its core components, enhancements, and advanced routing capabilities. {Lecture} Clock Structure and Layout Illustrates the clocking architecture and available resources in the Spartan UltraScale+ architecture and differentiates the clocking architectures of 7 series, UltraScale, and Spartan UltraScale+ FPGAs. {Lecture, Lab} I/O Resources: Overview Identifies some of the challenges of using high-speed I/O. Outlines the types and functions of I/O banks available in the Spartan UltraScale+ architecture. {Lecture} DSP Resources Explores the architecture and functionality of the DSP48E2 slice in Spartan UltraScale+ FPGAs. {Lecture} Transceivers Describes the advancements and features of Spartan UltraScale+ transceivers compared to previous UltraScale architectures. {Lecture} |
Please note: The instructor may change the content order to provide a better learning experience. Content may be updated prior to the workshop.
Prerequisites:
- Basic knowledge of AMD FPGAs and adaptive SoCs
- Basic knowledge of the Vivado and Vitis tools