DSP Design Using System Generator

NOTE: DSP core modules are now taught as DAY 1 in our Vitis Model Composer: A MATLAB and Simulink-based Product. Please view that class for available dates.

COURSE CODE: DSP-SYSGEN

Explore the Model Composer and System Generator tool and gain the expertise needed to develop advanced, low-cost DSP designs.

This course focuses on:

Implementing DSP functions using System Generator for DSP
Utilizing design implementation tools
Verifying through hardware co-simulation

For more about the System Generator for DSP, click here.

See Course Outline

2-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1200	12
In-Person Public Registration - $600/day	$1200	12
Printed Course Book (A PDF book is included in the course fee)	$100	1
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

See available dates for the Vitis Model Composer course

Training Duration:

2 Days

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Who should attend:

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB and Simulink software and want to use Xilinx System Generator for DSP design.

Software Tools

Vivado Design Suite System Edition
Model Composer and System Generator
Vitis HLS tool 2020.2
Vitis unified software platform
MATLAB with Simulink software

Hardware

Architecture: 7 series and UltraScale FPGAs
Demo board: Kintex UltraScale FPGA KCU105 board and Zynq UltraScale+ MPSoC ZCU104 board

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the System Generator design flow for implementing digital signal processing (DSP) functions
Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation
List various low-level and high-level functional blocks available in System Generator
Run hardware co-simulation
Identify the high-level blocks available for FIR and FFT designs
Implement multi-rate systems in System Generator
Integrate System Generator models into the Xilinx Vivado IDE
Design a processor-controllable interface using System Generator for DSP
Generate IPs from C-based design sources for use in the System Generator environment
Create and simulate designs using Model Composer

Course Outline

Day 1	Day 2
Introduction to System Generator Simulink Software Basics LAB: Using the Simulink Software Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate. Basic Xilinx Design Capture Demo: System Generator Gateway Blocks LAB: Getting Started with Xilinx System Generator Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board. Signal Routing LAB: Signal Routing Design padding and unpadding logic by using signal routing blocks. Implementing System Control LAB: Implementing System Control Design an address generator circuit by using blocks and Mcode.	Multi-Rate Systems LAB: Designing a MAC-Based FIR Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board. Filter Design LAB: Designing a FIR Filter Using the FIR Compiler Block Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board. System Generator, Vivad Design Suite, and Vivado HLS Integration LAB: System Generator and Vivado IDE Integration Embed System Generator models into the Vivado IDE. Kintex-7 FPGA DSP Platforms LAB: System Generator and Vivado HLS Tool Integration Generate IP from a C-based design to use with System Generator. LAB: AXI4-Lite Interface Synthesis Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq^® All Programmable SoC processor system.

Day 1

Day 2

Introduction to System Generator
Simulink Software Basics
LAB: Using the Simulink Software
Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
Basic Xilinx Design Capture
Demo: System Generator Gateway Blocks
LAB: Getting Started with Xilinx System Generator
Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
Signal Routing
LAB: Signal Routing
Design padding and unpadding logic by using signal routing blocks.
Implementing System Control
LAB: Implementing System Control
Design an address generator circuit by using blocks and Mcode.

Multi-Rate Systems
LAB: Designing a MAC-Based FIR
Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
Filter Design
LAB: Designing a FIR Filter Using the FIR Compiler Block
Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
System Generator, Vivad Design Suite, and Vivado HLS Integration
LAB: System Generator and Vivado IDE Integration
Embed System Generator models into the Vivado IDE.
Kintex-7 FPGA DSP Platforms
LAB: System Generator and Vivado HLS Tool Integration
Generate IP from a C-based design to use with System Generator.
LAB: AXI4-Lite Interface Synthesis
Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq^® All Programmable SoC processor system.

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Experience with the MATLAB and Simulink software
Basic understanding of sampling theory

Related Courses:

Updated 8-18-2024

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