Designing with Versal AI Engine: DSP Applications

COURSE CODE: AIE-DSP

This course covers the AMD Versal™ AI Engine architecture and using the AI Engine DSP Library, system partitioning, rapid prototyping, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using the AMD Vitis™ Model Composer is also demonstrated.

The emphasis of this course is on:

Providing an overview of the AI Engine architecture
Utilizing the Vitis DSP library for AI Engines
Performing system partitioning and planning
Adding custom kernel code for designs
Creating AI Engine DSP designs using the Vitis Model Composer
Analyzing reports using the Analysis view of the Vitis Unified IDE

See Course Outline

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$600	6
In-Person Registration - $600/day	$600	6
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee)	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

1 Day

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

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Who should attend:

DSP users, software and hardware developers, system architects, and anyone who needs to accelerate their software
applications using our devices.

Software Tools

Vitis Unified IDE
Vitis Model Composer

Hardware

Architecture: Versal adaptive SoC

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe the AMD Versal AI Engine architecture
Utilize the AI Engine DSP library and create a filter design with the AMD Vitis Unified IDE
Follow the system partitioning and system mapping methodology
Add custom kernel code to a design
Design a DSP function with the Vitis Model Composer AI Engine library
Analyze AI Engine designs using the Analysis view (Vitis Analyzer utility) of the Vitis Unified IDE

Course Outline

Day 1
AMD Versal AI Engine Architecture Introduces the architecture of the AI Engine and its components. {Lecture} Introduction to the AI Engine DSP Library Provides an overview of the AI Engine DSP library, which enables faster development and comes with ready-to-use example design that help with using the library and tools. {Lecture, Labs} System Partitioning Methodology Covers the system design planning and partitioning methodology for mapping design requirements to the AI Engine. {Lecture, Lab} Rapid Prototyping and Custom Coding of AI Engine Kernels Describes the AI Engine programming flow with kernels and Adaptive Data Flow (ADF) graphs. Also outlines the kernel coding methodology for writing custom kernel code and rapid prototyping. {Lecture, Lab} Overview of AI Engine Kernel Optimization Highlights the various AI Engine kernel optimization techniques, such as compiler directives, software pipelining, coding for performance, and core utilization. {Lecture} Analyzing AI Engine Design Reports Using the Vitis Unified IDE Covers the different reports generated by the Vitis Unified IDE and how to use these reports to optimize and debug AI Engine kernels. {Lecture} AI Engine DSP Designs with Vitis Model Composer Describes the Vitis Model Composer tool and how to use the libraries available with the tool for AI Engine DSP design development. {Lecture, Lab}

Day 1

AMD Versal AI Engine Architecture
Introduces the architecture of the AI Engine and its components. {Lecture}

Introduction to the AI Engine DSP Library
Provides an overview of the AI Engine DSP library, which enables faster development and comes with ready-to-use example design that help with using the library and tools. {Lecture, Labs}

System Partitioning Methodology
Covers the system design planning and partitioning methodology for mapping design requirements to the AI Engine. {Lecture, Lab}

Rapid Prototyping and Custom Coding of AI Engine Kernels
Describes the AI Engine programming flow with kernels and Adaptive Data Flow (ADF) graphs. Also outlines the kernel coding methodology for writing custom kernel code and rapid prototyping. {Lecture, Lab}

Overview of AI Engine Kernel Optimization
Highlights the various AI Engine kernel optimization techniques, such as compiler directives, software pipelining, coding for performance, and core utilization. {Lecture}

Analyzing AI Engine Design Reports Using the Vitis Unified IDE
Covers the different reports generated by the Vitis Unified IDE and how to use these reports to optimize and debug AI Engine kernels. {Lecture}

AI Engine DSP Designs with Vitis Model Composer
Describes the Vitis Model Composer tool and how to use the libraries available with the tool for AI Engine DSP design development. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Familiarity with the C/C++ programming language
Vitis tool for acceleration development flow
Familiarity with basic signal processing concepts
Basic knowledge of Versal AI Engine architecture and programming

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Updated 08-29-2025

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