Designing with the Versal AI Edge Series Gen 2 and Prime Gen 2

Designing with Versal AI Edge Series Gen 2: AIE-ML v2 Architecture and Design Flow

COURSE CODE: AIE-MLV2-ARCH

This course outlines the architecture of AMD Versal™ AI Engine ML v2 (AIE-ML v2), a part of AMD Versal AI Edge Series Gen 2 devices, and explores the features and key architectural enhancements with this iteration of AI Engines.

This course provides an overview of both native and supported data types and highlights how to program the AI Engine and migrate older AI Engine designs. The enhancements included in AIE-ML v2, utilizing the DSP libraries, along with the compute capabilities and how to analyze performance, will also be demonstrated.

The emphasis of this course is on:

Providing an overview of the new AI Engine (AIE-ML v2) architecture
Describing the system design planning and application partitioning methodology
Describing the AMD Vitis™ and AI Engine tool flow
Providing an overview of the native and supported data types for functional implementation in AIE-ML v2
Illustrating the programming model and the usage of shared buffers (memory tiles) for the AIE-ML v2
Utilizing the Vitis DSP library for AI Engines in implementing a matrix multiplication with multiple tiles
Analyzing reports using the Vitis Analysis view and reviewing throughput and performance

See Course Outline

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$600	6
In-Person Registration - $600/day	$600	6
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee)	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

1 Day

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

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Who should attend:

DSP users, software developers, system architects, and anyone who needs to accelerate their software applications using our devices

Software Tools

Vitis Unified IDE
Optional: MATLAB tool (any latest version)

Hardware

Architecture: Versal adaptive SoC

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe the AMD Versal AI Engine AIE-ML v2 architecture
Follow the system partitioning and system mapping methodology
Describe the AI Engine tool flow and utilize the supported data types for AIE-ML v2
Program the AI Engines with the help of the programming model and describe the utilization of memory tiles
Utilize the AI Engine DSP library and test a matrix multiplication design with multiple tiles for parallelization
Analyze AI Engine designs using the Analysis view (Vitis Analyzer utility) and analyze throughput and performance

Course Outline

Day 1
AMD Versal Adaptive SoC: Architecture Overview Provides a high-level overview of the Versal architecture, illustrating the various compute resources available in the Versal architecture. {Lecture} Introduction to the AIE-ML v2 Architecture Discusses the AI Engine AIE-ML v2 array architecture and its tiles. Also lists the key differences between the AIE, AIE-ML, and AIE-ML v2 architectures. {Lecture} Versal AI Edge Series Gen 2: Application Partitioning Covers the system design planning and partitioning methodology. Also explains what application partitioning is and how an application can be accelerated by using various compute domains in the Versal device. {Lecture} Versal AI Edge Series Gen 2: AIE-ML v2 Tool Flow Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Lab} Supported Data Types for AIE-ML v2 Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. Covers the vector-based floating-point data types and block floating-point data types. {Lecture} The Programming Model and AIE-ML v2 Memory Tiles Highlights the basics of AI Engine kernels and graph code as well as the data flow graph model. Also describes the memory tiles in the AIE-ML v2 architecture and illustrates AI Engine-ML v2 programming using both shared buffers and external buffers with the AIE-ML v2. {Lecture, Lab} Overview of the AI Engine DSP Library with AIE-ML v2 Provides an overview of the AI Engine DSP library, which enables faster development and comes with ready-to-use example designs that help with using the library and tools. Also describes how to use and configure the library functions. {Lecture, Lab} Analyzing the AI Engine Design Reports and Performance Covers the different reports generated by the Analysis View in the Vitis Unified IDE and how to use these reports to optimize AI Engine designs. Also shows how to compare performance improvements. {Lecture, Lab}

Day 1

AMD Versal Adaptive SoC: Architecture Overview
Provides a high-level overview of the Versal architecture, illustrating the various compute resources available in the Versal architecture. {Lecture}

Introduction to the AIE-ML v2 Architecture
Discusses the AI Engine AIE-ML v2 array architecture and its tiles. Also lists the key differences between the AIE, AIE-ML, and AIE-ML v2 architectures. {Lecture}

Versal AI Edge Series Gen 2: Application Partitioning
Covers the system design planning and partitioning methodology. Also explains what application partitioning is and how an application can be accelerated by using various compute domains
in the Versal device. {Lecture}

Versal AI Edge Series Gen 2: AIE-ML v2 Tool Flow
Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform. {Lecture, Lab}

Supported Data Types for AIE-ML v2
Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions. Covers the
vector-based floating-point data types and block floating-point data types. {Lecture}

The Programming Model and AIE-ML v2 Memory Tiles
Highlights the basics of AI Engine kernels and graph code as well as the data flow graph model. Also describes the memory tiles in the AIE-ML v2 architecture and illustrates AI Engine-ML v2
programming using both shared buffers and external buffers with the AIE-ML v2. {Lecture, Lab}

Overview of the AI Engine DSP Library with AIE-ML v2
Provides an overview of the AI Engine DSP library, which enables faster development and comes with ready-to-use example designs that help with using the library and tools. Also describes how to use and configure the library functions. {Lecture, Lab}

Analyzing the AI Engine Design Reports and Performance
Covers the different reports generated by the Analysis View in the Vitis Unified IDE and how to use these reports to optimize AI Engine designs. Also shows how to compare performance improvements. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Familiarity with the C/C++ programming language
Vitis tool for acceleration development flow
Familiarity with basic signal processing concepts

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Updated 08-29-2025

©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.