Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2

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Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2

COURSE CODE: VER2-ARCH

Learn about the AMD Versal AI Edge Series Gen 2 and Prime Series Gen 2 adaptive SoC architectures, which combine programmable logic with a new high-performance processing system and next-generation AI Engines. Also learn how these devices facilitate end-to-end acceleration and maximize system performance for embedded systems — all in a single device built on a foundation of enhanced safety and security.

The emphasis of this course is on:

  • Describing the different compute resources available in the Versal adaptive SoC
  • Explaining the new high-performance processing system (PS)
  • Describing the next-generation AI Engine architecture
  • Describing the network on chip (NoC) resources
  • Outlining the available DDR5/LPDDR5X memory controller support
  • Reviewing the new image and video processing hard blocks
  • Explaining the functional safety and security enhancements
  • Identifying the available PCI Express

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$2002

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

3 Days

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I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

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Who should attend:

Software and hardware developers, system architects, and anyone who wants to learn about the architecture of the Versal AI Edge Series Gen 2 and Prime Series Gen 2 devices.

Software Tools

  • Vivado Design Suite 2025.1
  • Vitis Unified IDE 2025.1

Hardware

  • Architecture: Versal adaptive SoC

Skills Gained

After completing this comprehensive training, you will have the necessary skills to: 

  • Describe the different compute resources available in the AMD Versal adaptive SoC
  • Explain the new high-performance processing system (PS)
  • Describe the next-generation AI Engine architecture
  • Describe the programmable network on chip (NoC) resources
  • Outline the available DDR5/LPDDR5X memory controller support
  • Describe the new image and video processing hard blocks
  • Explain the functional safety and security enhancements
  • Identify the available PCI Express Gen 5 and 32G high-speed serial transceiver solutions

Course Outline

Day 1Day 2Day 3
Introduction and Portfolio Overview
Describes the need for Versal devices and offers an overview of the Versal portfolio. {Lecture}

Architecture Overview
Provides a high-level overview of the Versal architecture, illustrating the various compute resources available in the Versal architecture. {Lecture}

Design Tool Flow
Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}

Programmable Logic (PL)
Describes the logic resources available in the programmable logic. Also discusses the clocking architecture, clock buffers, clock routing, and clock de-skewing options. {Lecture}

SelectIO Resources
Describes the I/O bank, SelectIO interface, and I/O delay features. {Lecture}		Processing System
Reviews the Arm Cortex-A78AE processor APU and CortexR52 processor RPU that form the processing system. Also discusses high-speed connectivity, boot modes, system peripherals, and power domains. {Lecture}

Platform Management Controller (PMC)
Describes the platform management controller architecture and the role of platform loader and manager (PLM) in the Versal device boot process. {Lecture}

Boot and Configuration
Covers the boot phases, flows, and modes along with the process of generating a boot image. Also discusses the concept and benefits of segmented configuration. {Lecture}

AIE-ML v2 Architecture Overview
Discusses the AI Engine AIE-ML v2 array architecture and its tiles. Also lists the key differences between the AIE, AIE-ML, and AIE-ML v2 architectures. {Lecture, Lab}

NoC Architecture
Covers the reasons to use the network on chip, the NoC architecture and its basic elements, design entry flows, and common terminology. {Lecture]		Designing with DDR5
Describes the DDR5 memory controller features and its configuration flow. Also demonstrates how to tune a design to increase efficiency. {Lecture, Lab}

Multimedia Hard Blocks
Reviews the multimedia-specific hard IP blocks such as VCU2, GPU, and ISP available in the Versal devices. {Lecture}

Security and Functional Safety Overview
Describes the security architecture and the available security units. Also provides an overview of the increased embedded system security. {Lecture}

PCI Express Solutions
Provides an overview of the PCIe® module and describes the PL and MDB PCIe blocks. {Lecture, Lab}

Serial Transceivers
Describes the transceivers in the Versal device. Also introduces the new GT Wizard Subsystem flow. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Basic knowledge of AMD FPGAs and adaptive SoCs
  • Basic knowledge of the AMD Vivado and Vitis tools

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Updated 08-29-2025
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