Designing with the Versal Adaptive SoC: Serial Transceivers

COURSE CODE: ACAP-TRX

This course provides a system-level understanding of AMD Versal adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB design issues is also covered.

The focus is on:

Constructing a system using Versal device serial transceivers by:
Selecting the appropriate IP for an application
Configuring Transceivers Wizard IPs
Using transceiver IP example designs
Simulating and implementing transceiver IPs
Identifying the advanced capabilities of the serial transceivers, including using IBERT and eye scan options
Accessing the appropriate reference material for board design issues involving signal integrity, the power supply, reference clocking, and trace design

See Course Outline

1-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$600	6
In-Person Registration - $600/day	$600	6
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee)	$200	2

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

1 Day

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

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Who should attend:

Hardware designers who want to create applications using serial transceivers
System architects who want to leverage the key advantages of serial transceivers

Software Tools

Vivado Design Suite

Hardware

Architecture: Versal adaptive SoC
Evaluation board: Versal VCK190 / VPK120 boards

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Describe and utilize the building blocks of the serial transceivers in the AMD Versal devices
Describe and utilize the ports and attributes of the transceivers
Design, simulate, and implement the transceivers
Utilize transceiver debugging options
Identify transceiver use cases
Describe transceiver board design requirements

Course Outline

Day 1
Course Introduction Introduces the course and discusses serial transmission. {Lecture} Serial Transceiver Shared Features Describes the structure and shared features, such as clocking and reset schemes, of the Versal device serial transceivers. {Lecture} Serial Transceiver Architecture Discusses the architecture and functionality of the transmit and receive functional blocks. {Lecture} Transceiver IP Generation Demonstrates usage of the Transceivers Wizard. {Lecture, Lab} Transceiver IP Simulation Covers how to perform transceiver design simulation. {Lecture, Lab} Transceiver IP Implementation Illustrates how to perform transceiver implementation and verification on real hardware. {Lecture, Lab targeting the VCK190 board} Transceiver Use Cases Discusses using the transceivers for several protocol applications, including the PCI Express®, Ethernet, Interlaken, JESD204, and Aurora interfaces. {Lecture} Transceiver Board Design Describes board design issues involving signal integrity, the power supply, reference clocking, and trace design. {Lecture} GTM Transceiver Reviews GTM transceiver-specific design generation, simulation, implementation, and verification on real hardware. {Lecture, Labs targeting the VPK120 board}

Day 1

Course Introduction
Introduces the course and discusses serial transmission. {Lecture}

Serial Transceiver Shared Features
Describes the structure and shared features, such as clocking and reset schemes, of the Versal device serial transceivers. {Lecture}

Serial Transceiver Architecture
Discusses the architecture and functionality of the transmit and receive functional blocks. {Lecture}

Transceiver IP Generation
Demonstrates usage of the Transceivers Wizard. {Lecture, Lab}

Transceiver IP Simulation
Covers how to perform transceiver design simulation. {Lecture, Lab}

Transceiver IP Implementation
Illustrates how to perform transceiver implementation and verification on real hardware. {Lecture, Lab targeting the VCK190 board}

Transceiver Use Cases
Discusses using the transceivers for several protocol applications, including the PCI Express®, Ethernet, Interlaken, JESD204, and Aurora interfaces. {Lecture}

Transceiver Board Design
Describes board design issues involving signal integrity, the power supply, reference clocking, and trace design. {Lecture}

GTM Transceiver
Reviews GTM transceiver-specific design generation, simulation, implementation, and verification on real hardware. {Lecture, Labs targeting the VPK120 board}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

Knowledge of Verilog or VHDL
Familiarity with logic design (state machines and synchronous design)
Some experience with AMD Vivado implementation
Some experience with a simulation tool, preferably the Vivado simulator
Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

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Updated 08-29-2025

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