Designing and Verification with SystemVerilog
Designing and Verification with SystemVerilog
COURSE CODE: BLT-SV-DV
This comprehensive course is a thorough introduction to SystemVerilog constructs for design and verification. It is a combination of the instructional material found in Designing with SystemVerilog and Verification with SystemVerilog.
The emphasis is on:
- Writing RTL code using the new constructs available in SystemVerilog
- Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
- Targeting and optimizing AMD FPGAs and adaptive SoC devices using SystemVerilog
- Writing testbenches to verify a design under test (DUT) utilizing the constructs available in SystemVerilog
- Reviewing object-oriented modeling, data types, reusable tasks and functions, randomization, code coverage, assertions, the Direct Programming Interface (DPI), and interprocess communication
In this three-day course, you will gain valuable hands-on experience with practical lab exercises to reinforce key concepts. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently develop and verify RTL designs.
| 3-Day Instructor-led Course | Price USD | Training Credits |
|---|---|---|
| Hosted Online - $600/day | $1800 | 18 |
| In-Person Public Registration - $600/day | $1800 | 18 |
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration. | $100 | 1 |
| Private Training | Learn More | Learn More |
| Coaching | Learn More | Learn More |
Scheduled Classes
Live Online Training (9am-5pm ET)
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Who should attend:
Hardware designers and engineers, logic designers, and verification engineers.
Software Tools
- Vivado Design Suite
Hardware
- Architecture: N/A*
- Demo board: Zynq UltraScale+ MPSoC ZCU104 board*
* This course does not focus on any particular architecture.
Skills Gained
After completing this comprehensive training, you will know how to:
- Describe the features and benefits of using SystemVerilog for designing RTL
- Identify the new data types supported in SystemVerilog
- Use an enumerated data type for coding a finite state machine (FSM)
- Explain how to use structures, unions, and arrays
- Describe the new procedural blocks and analyze the affected synthesis results
- Define the enhancements and ability to reuse tasks, functions, and packages
- Identify how to simplify module definitions and instantiations using interfaces
- Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
- Target and optimize AMD FPGAs and adaptive SoCs by using SystemVerilog
- Synthesize and analyze SystemVerilog designs with the Vivado Design Suite
- Download a complete SystemVerilog design to an evaluation board
- Describe the advantages and enhancements to SystemVerilog to support verification
- Define the new data types available in SystemVerilog
- Analyze and use the improvements to tasks and functions
- Discuss and use the various new verification building blocks available in SystemVerilog
- Describe object-oriented programming and create a class-based verification environment
- Explain the various methods for creating random data
- Create and utilize random data for generating stimulus to a DUT
- Identify how SystemVerilog enhances functional coverage for simulation verification
- Utilize assertions to quickly identify correct behavior in simulation
- Identify how the direct programming interface can be used with C/C++ in a verification environment
- Describe the interprocess communication and threads
Course Outline
| Day 1 | Day 2 | Day 3 |
|---|---|---|
| Introduction to SystemVerilog Provides an introduction to the SystemVerilog language. {Lecture} Data Types Describes the data types supported by SystemVerilog. {Lecture, Demo, Lab} User-Defined and Enumerated Data Types Reviews the user-defined and enumerated data types supported by SystemVerilog. {Lecture} Type Casting Explains type casting in SystemVerilog. {Lecture} Arrays and Strings Covers the use of arrays in SystemVerilog. {Lecture} SystemVerilog Building Blocks Describes the design and verification building blocks in SystemVerilog. {Lecture} Structures Illustrates the use of structures in SystemVerilog. {Lecture, Lab} Unions Reviews the use of unions in SystemVerilog. {Lecture, Lab} Additional Operators in SystemVerilog Describes the operators supported by SystemVerilog beyond those found in Verilog. {Lecture} | Procedural Statements Highlights the different procedural blocks provided by SystemVerilog. {Lecture, Lab} Control Flow Statements Investigates the different control statements provided by SystemVerilog. {Lecture} Functions Explains the SystemVerilog enhancements to functions. {Lecture} Tasks Describes the task SystemVerilog construct. {Lecture} Packages Describes the package SystemVerilog construct. {Lecture, Lab} Interfaces Describes the concept of interfaces in SystemVerilog. {Lecture} Targeting AMD FPGAs and Adaptive SoCs Focuses on AMD-specific implementation and chip-level optimization. {Lecture, Lab} Introduction to SystemVerilog for Verification Provides an introduction to the SystemVerilog language. {Lecture} Data Types Explains SystemVerilog data types and arrays, such as fixed-size arrays, dynamic arrays, and associative arrays. {Lecture} | Tasks and Functions Reviews SystemVerilog tasks and functions {Lecture, Lab} SystemVerilog Verification Building Blocks Describes SystemVerilog verification building blocks, such as program, interface, clocking, and packages. {Lecture, Lab} Object-Oriented Modeling Introduces object-oriented modeling, such as encapsulation, inheritance, and polymorphism. {Lecture, Lab} Randomization Illustrates randomization methods, such as randcase, random sequence, and class-based randomization. {Lecture, Lab} Coverage Describes functional coverage and usage of covergroup, coverpoint, and bins. {Lecture, Lab} Assertions Reviews the different types of assertions. {Lecture, Lab} Direct Programming Interface Introduces the Direct Programming Interface (DPI) for interacting with C languages. {Lecture, Demo} Interprocess Communication Describes the interprocess communication between the different processes used to model a complex system. {Lecture} |
Please note: The instructor may change the content order to provide a better learning experience.