High-Level Synthesis with the Vitis Unified

High-Level Synthesis with the Vitis Unified IDE

COURSE CODE: DSP-HLS

This course provides a thorough introduction to high-level synthesis (HLS) using the AMD Vitis™ Unified IDE.

The focus of this course is on:

Converting C/C++ designs into RTL implementations
Learning the HLS component development flow
Creating I/O interfaces for designs
Applying different optimization techniques to designs
Improving throughput, area, latency, and logic by using different HLS pragmas/directives
Exporting IP that can be used with the Vivado™ IP catalog
Migrating designs from the classic Vitis HLS tool to the Vitis Unified IDE

3-Day Instructor-led Course	Price USD	Training Credits
Hosted Online - $600/day	$1800	18
In-Person Public Registration - $600/day	$1800	18
Private Training	Learn More	Learn More
Coaching	Learn More	Learn More
Printed Course Book (A PDF book is included in the course fee) Cannot be purchased without registration.	$200	2

Scheduled Classes

Live Online Training (Starts at 9am ET)

March 31 - April 2, 2026 | Register Today

View our Full Calendar for class date status.

(Confirmed, Closed, Full)

Training Duration:

3 Days

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

This one was definitely one of the best

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

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Who should attend:

Software and hardware engineers who are looking to utilize high-level synthesis.

Software Tools

Vitis IDE
Vivado Design Suite

Hardware

Architecture: Zynq UltraScale+ MPSoC and Versal AI Core series
Demo board: Zynq UltraScale+ MPSoC ZCU104 board*

* This course focuses on the Zynq UltraScale+ MPSoC architecture.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Enhance productivity by using the AMD Vitis Unified IDE for HLS component development
Describe the HLS component development flow
Use the Vitis Unified IDE to create an HLS component
Identify common coding pitfalls as well as methods for improving RTL/hardware code
Use directives/pragmas to improve throughput, area, latency, and logic and to select RTL interfaces
Perform system-level integration of IP generated by the Vitis Unified IDE
Migrate designs from the classic Vitis HLS tool to the Vitis Unified IDE

Course Outline

Day 1	Day 2	Day 3
Introduction to High-Level Synthesis Provides an overview of high-level synthesis (HLS), the Vitis Unified IDE for HLS flow, and the verification advantage. {Lecture} HLS Component Development Flow Explores the HLS component development flow in the Vitis Unified IDE. {Lecture, Lab} Abstract Parallel Programming Model for HLS Describes the structuring of a design at a high level using an abstract parallel programming model. {Lecture} Design Exploration with Directives Explores different optimization techniques that can improve design performance. {Lecture} HLS Component Development Using the Command Line Describes the unified command line interface and the v++ and vitis-run commands. {Lecture, Lab} Introduction to Vitis HLS Design Methodology Introduces the methodology guidelines covered in this course and the HLS Design Methodology steps. {Lecture} Introduction to I/O Interfaces Explains interfaces such as the block-level and port-level protocols abstracted by Vitis HLS from a C design. {Lecture} Block-Level Protocols Explains the different types of block-level protocols abstracted by Vitis HLS. {Lecture, Lab} Port-Level I/O Protocols Describes the port-level interface protocols abstracted by Vitis HLS from a C design. {Lecture, Labs}	AXI Adapter Interface Protocols Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by Vitis HLS. {Lecture} Vitis HLS Code Analyzer Provides an overview of the Vitis Code Analyzer, its features, and how to view generated reports. {Lecture, Lab} Optimizing for Performance: PIPELINE Describes the PIPELINE directive for improving the throughput of a design. {Lecture, Lab} Optimizing for Performance: DATAFLOW Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible. {Lecture, Lab} Optimizing for Throughput Describes the performance limitations caused by arrays in a design. Also explores optimization techniques to handle arrays for improving performance. {Lecture, Lab} Optimizing for Latency: Default Behavior Describes the default behavior of Vitis HLS on latency and throughput. {Lecture} Optimizing for Latency: Reducing Latency Describes how to optimize the C design to improve latency. {Lecture}	Optimizing for Area and Logic Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization. {Lecture, Lab} Optimizing AXI System Performance Describes AXI burst transfers and their types. Also outlines the optimization steps to improve system performance. {Lecture} Vitis HLS Performance Pragma Explains the Vitis HLS Performance pragma and details its step-by-step methodology for achieving performance targets. {Lecture} Vitis HLS Libraries Describes the library support offered by Vitis HLS. {Lecture} Vitis HLS Libraries: Arbitrary Precision Data Types Describes Vitis HLS support for the C/C++ languages as well as arbitrary precision data types. {Lecture, Lab} Using Pointers in Vitis HLS Explains the use of pointers in a design and workarounds for some of the limitations. {Lecture} HLS Component Design Flow – System Integration Illustrates the process of developing and exporting an HLS component as Vivado IP. {Lab} Migrating to the Vitis Unified IDE – HLS Component Describes the need for the Vitis Unified IDE and identifies different approaches for migrating projects from the classic Vitis HLS tool to the Vitis Unified IDE. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

C or C++ knowledge
Basic RTL design flow knowledge

RELATED COURSES:

Updated 08-29-2025

©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

High-Level Synthesis with the Vitis Unified IDE