Adaptive SoCs for System Architects

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Adaptive SoCs for System Architects

COURSE CODE: MPSOC-ACAP-SA

This course provides system architects with an overview of the capabilities and support for the AMD Zynq UltraScale+ MPSoC and Versal adaptive SoC devices.

The emphasis is on:

  • Utilizing power management strategies effectively
  • Leveraging the platform management unit (PMU) capabilities
  • Running the system securely and safely
  • Reviewing the high-level architecture of the devices
  • Identifying appropriate boot sequences

See Course Outline

3-Day Instructor-led CoursePrice USDTraining Credits
Hosted Online - $600/day$180018
In-Person Public Registration - $600/day$180018
Private TrainingLearn MoreLearn More
CoachingLearn MoreLearn More
Printed Course Book (A PDF book is included in the course fee)
Cannot be purchased without registration.
$2002

Scheduled Classes

No Scheduled Sessions - Contact Us to ask about setting one up!

Training Duration:

3 Days

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A lot of insights beyond the course

Glenn was a great instructor and provided us with a lot of insights beyond the course material

– Student from Embedded Design with PetaLinux Tools

All in all a great experience

Tom was a great instructor, very knowledgeable and polite throughout the course. All in all a great experience.

– Student from Vivado Boot Camp for the FPGA User Phase 2

The instructor was excellent

The instructor for this class, Glenn, was excellent. He presented the material with great examples and encouraged students to ask questions at any point in the course. Whenever there was a question he could not answer, he mentioned that he would bring it to his colleagues for answers, and after we came back from lunch, he had the answer.

– Student from Embedded Design with PetaLinux Tools

This one was definitely one of the best

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Knowledgeable instructor

Elie was a knowledgeable instructor, and did a really good job of making sure students were comfortable interrupting for questions. He answered questions well and communicated very clearly.

– Student from Designing with VHDL

They had answers for just about every question

Erich and Nathaniel were great, they had answers for just about every question/issue and linked relevant Xilinx/Vivado user manuals for further explanation/documentation.

– Student from Vivado Boot Camp for the FPGA User Phase 2

Labs were great

The labs were great and really reinforced the topics.

– Student from Designing with Versal AI Engine 1: Architecture and Design Flow

My instructor took time

My instructor took time during some of the breaks to look up and distribute information about questions that he didn’t happen to know direct answers to, and I always appreciate when instructors take the time to do that.

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very capable

My instructor was very capable of answering any of my questions even when they were an extension of the material being presented. If he wasn’t sure of an answer, he made sure to verify his thoughts before answering my question

– Student from Vivado Boot Camp for the FPGA User Phase 1

Thanks for a great class!

I have attended a bunch of training courses over the years. This one was definitely one of the best I have attended. Erich did a great job, and the material is very well done. Thanks for a great class!

– Student from Vivado Boot Camp for the FPGA User Phase 1

College course fit into 3 days

The instructor certainly knew the material and could explain the concepts as well as answer questions. Even the instructor said that this is a college course fit into 3 days.

– Student from Designing with VDHL

I gained a lot of information

The class was pretty great and I gained a lot of information from it that I will certainly be applying at my job going forward!!

– Student from Vivado Boot Camp for the FPGA User Phase 1

Expert tidbits

I liked the expert tidbits my instructor threw in to keep in mind when working on projects in the future regarding best practices. I also appreciated the questions the more experienced students asked, and how he was knowledgeable in order to address them.

– Student from Designing with VHDL

Erich was engaging

Erich was engaging and had good pacing during the course. Although the course was all day for 3 days I didn’t feel exhausted at the end of sessions.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Elie was an exceptional instructor

Elie was an exceptional instructor, and I would welcome the opportunity to take another class from him and BLT in the future.

– Student from Designing with Verilog

Can quickly and concisely answer technical questions

I really like the expertise of the presenters and that they can quickly and concisely answer technical questions, Tom did great!

– Student from Vivado Boot Camp for the FPGA User Phase 3

My instructor was very professional

My instructor was very professional and answered all of my questions thoroughly. I enjoyed hearing about his professional experience with certain aspects of the course / labs as we went through the course.

– Student from Vivado Boot Camp for the FPGA User Phase 1

Impressed with the effort

Glenn is a good instructor – I’m impressed with the effort he put into the presentation.
I hope I didn’t annoy him with too many questions.

– Student from Designing with Versal AI Engine 3: Kernel Programming and Optimization

I have a great grasp of HLS and how to use Vitis effectively

I really enjoyed this class and feel like I have a great grasp of HLS and how to use Vitis effectively. Cole was a great instructor, and I
would easily take another class with him. Thank you very much for running this class!

– Student from High-Level Synthesis with the Vitis HLS Tool

I would endorse him to teach a friend

Cole was a fantastic instructor and was very proactive in answering any questions that came up. I would endorse him to teach if a friend had to learn from this course.

– Student from Designing with Verilog

One of the best experiences for AMD Xilinx training that I’ve had

Bill was a great instructor and answered all of our questions. He went above and beyond to make this course a great experience. If/When I use BLT for Xilinx training in the future I will be on the lookout to see if he’s leading the lecture. One of the best experiences for AMD Xilinx training that I’ve had.

– Student from Designing with VHDL

I had a wonderful instructor

I had a wonderful instructor. His pacing throughout the course was good and made sure to allow for student questions and have conversations about related topics and experiences. I think the atmosphere was great for everyone to both learn and to share experiences, tips, and tricks about using the tool and the features discussed throughout the course.

– Student from Vivado Boot Camp for the FPGA User Phase 3

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Who should attend:

System architects interested in understanding the capabilities and ecosystem of the Zynq UltraScale+ MPSoC and Versal adaptive SoC devices.

Software Tools

  • Vivado Design Suite 2024.1
  • Vitis Unified IDE 2024.1
  • Hardware emulation environment:
    •  VirtualBox
    • QEMU
    • Ubuntu desktop
    • PetaLinux

Hardware

  • Zynq UltraScale+ MPSoC ZCU104 board
  • Versal adaptive SoC VCK190 board

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Effectively use power management strategies and leverage the capabilities of the platform management unit (PMU)
  • Identify mechanisms to secure and safely run the system
  • Outline the high-level architecture of the devices
  • Define the boot sequences appropriate to system requirements

Course Outline

Day 1Day 2Day 3
Zynq UltraScale+ MPSoC Overview
Overview of the Zynq UltraScale+ MPSoC device. {Lectures, Demo, Lab}

QEMU
Introduction to the Quick Emulator, which is the tool used to run software for the adaptive SoC device when hardware is not available. {Lectures, Demo, Lab}

Safety and Security
Defines what safety and security is in the context of embedded systems and introduces several standards. {Lectures, Demo}		Power Management
Overview of the PMU and the power-saving features of the device. {Lectures, Demo, Lab}

System Coherency
Learn how information is synchronized within the API and through the ACE/AXI ports. {Lectures}

DDR and QoS
Understand how DDR can be configured to provide the best performance for your system. {Lectures, Demo, Lab}		Adaptive SoC Booting
Demonstrates how to implement the embedded system, including the boot process, boot image creation, and failure detection during boot. {Lectures, Labs}

Zynq UltraScale+ MPSoC: Ecosystem Support
Overview of supported operating systems, software stacks, hypervisors, etc. {Lecture}

Debugging Using Cross-Triggering
Illustrates how HW-SW cross-triggering techniques can uncover issues. {Lecture, Lab}

Please note: The instructor may change the content order to provide a better learning experience.

Prerequisites:

  • Suggested: Understanding of the Zynq 7000 SoC, Zynq UltraScale+ MPSoC, and/or Versal adaptive SoC architectures
  • Familiarity with embedded operating systems

RELATED COURSES:

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Updated 08-29-2025
©2025 Advanced Micro Devices, Inc. Xilinx, Inc. is now part of AMD. Xilinx, the Xilinx logo, AMD, the AMD Arrow logo, Alveo, Artix, Kintex, Kria, Spartan, Versal, Vitis, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Advanced Micro Devices, Inc.

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